专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5796638A Methods, apparatus and computer program products for synthesizing integrated circuits with electrostatic discharge capability and connecting ground rules faults therein 失效
标题翻译：用于合成具有静电放电能力的集成电路并校正其中的接地规则故障的方法，装置和计算机程序产品
公开(公告)号：US5796638A
公开(公告)日：1998-08-18
申请号：US668856
申请日：1996-06-24
申请人： Sung-Mo Steve Kang , Charvaka Duvvury , Carlos Hernando Diaz , Sridhar Ramaswamy
发明人： Sung-Mo Steve Kang , Charvaka Duvvury , Carlos Hernando Diaz , Sridhar Ramaswamy
IPC分类号： G06F17/50 , H01L27/02
CPC分类号： G06F17/5068 , H01L27/0248
摘要： A method, apparatus and computer program product for synthesizing and correcting ESD and EOS ground rules faults in integrated circuits generates a representation of a first functional circuit element (e.g., logic gate) connected to a representation of a first input/output (I/O) pad, via a representation of a first electrical path, and generates a representation of a first ESD circuit element connected to the representation of the first input/output pad via a representation of a second electrical path which may overlap a portion of the first electrical path. First and second sheet resistances (or quantities related thereto) of the first and second electrical paths, respectively, are determined and a length and/or width of the representation of at least one of the first and second electrical paths is adjusted if the first sheet resistance is greater than the second sheet resistance, so that the first sheet resistance is less than the second sheet resistance. Corners in representations of adjacent power rails are also detected, where these representations have opposing edges separated by a minimum rail spacing, and a position of at least one of the power rails relative to the other is adjusted so that the opposing edges are separated by a spacing which is no less than about two times the minimum rail spacing.
摘要翻译：用于在集成电路中合成和校正ESD和EOS接地规则故障的方法，装置和计算机程序产品产生连接到第一输入/输出（I / O）的表示的第一功能电路元件（例如，逻辑门）的表示）焊盘，经由第一电路径的表示，并且经由第二电路径的表示产生连接到第一输入/输出焊盘的表示的第一ESD电路元件的表示，该第二电路径可以与第一电路的一部分重叠路径。确定第一和第二电路径的第一和第二薄片电阻（或相关数量），并且如果第一薄片和第二电路径的第一和第二电路径的至少之一的表示的长度和/或宽度被调整，电阻大于第二薄层电阻，使得第一薄层电阻小于第二薄层电阻。还检测到相邻电力轨道表示的角，其中这些表示具有由最小轨道间隔分开的相对边缘，并且调节至少一个电力轨道相对于另一个的位置，使得相对边缘由间距不小于最小轨道间距的大约两倍。

2. 发明授权

US06548363B1 Method to reduce the gate induced drain leakage current in CMOS devices 有权
标题翻译：降低CMOS器件漏极漏电流的方法
公开(公告)号：US06548363B1
公开(公告)日：2003-04-15
申请号：US09547237
申请日：2000-04-11
申请人： Chung-Cheng Wu , Bi-Ling Lin , Carlos Hernando Diaz
发明人： Chung-Cheng Wu , Bi-Ling Lin , Carlos Hernando Diaz
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/7833
摘要： A method for forming FET devices with attenuated gate induced drain leakage current. There is provided a silicon semiconductor substrate employed within a microelectronics fabrication. There is formed within the silicon substrate field oxide (FOX) dielectric isolation regions defining an active silicon substrate device area. There is formed over the substrate a silicon oxide gate oxide insulation layer employing thermal oxidation. There is then formed over the silicon oxide gate oxide insulation layer a patterned polycrystalline silicon gate electrode layer. There is then thermally oxidized the substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and in the adjacent silicon substrate area. There is then etched back the thicker silicon oxide layer from the silicon substrate area adjacent to the gate electrode. There is then formed employing low energy ion implantation shallow junction source-drain extension regions adjacent to the gate electrode. There is then formed source-drain regions to complete the FET device, which exhibits attenuated drain leakage current. The present invention may be employed to fabricate complementary metal-oxide-silicon (CMOS) FET devices of either polarity with attenuated gate induced drain leakage (GIDL) current, short channel effect (SCE) and punch-through leakage current in integrated circuit microelectronics fabrications wherein low power drain is desired.
摘要翻译：一种用于形成具有衰减栅极感应漏极漏电流的FET器件的方法。提供了在微电子制造中使用的硅半导体衬底。形成硅衬底场氧化物（FOX）电介质隔离区域，限定有源硅衬底器件区域。在衬底上形成采用热氧化的氧化硅栅极氧化物绝缘层。然后在氧化硅栅极氧化物绝缘层上形成图案化的多晶硅栅极电极层。然后，将基板和多晶硅栅电极热氧化，以在栅电极的边缘和相邻的硅衬底区域中形成较厚的氧化硅层。然后从与栅电极相邻的硅衬底区域中回蚀更厚的氧化硅层。然后形成采用与栅电极相邻的低能离子注入浅结源极 - 漏极扩展区。然后形成源极 - 漏极区以完成FET器件，其表现出衰减的漏极漏电流。本发明可用于在集成电路微电子器件制造中制造具有衰减栅极感应漏极泄漏（GIDL）电流，短沟道效应（SCE）和穿通漏电流两种极性的互补金属氧化物 - 硅（CMOS）FET器件其中期望低功率消耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式