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1. 发明申请

US20150235633A1 MULTI-LAYER DISPLAY SYSTEM 审中-公开
标题翻译：多层显示系统
公开(公告)号：US20150235633A1
公开(公告)日：2015-08-20
申请号：US14185866
申请日：2014-02-20
申请人： Chanpreet Singh , Kshitij Bajaj , Michael A. Staudenmaier
发明人： Chanpreet Singh , Kshitij Bajaj , Michael A. Staudenmaier
IPC分类号： G09G5/39 , G06T9/00
CPC分类号： G09G5/001 , G09G5/14 , G09G5/363 , G09G2340/02 , G09G2340/12 , G09G2352/00 , G09G2360/06 , H04N19/42 , H04N19/44
摘要： A multi-layer display system for displaying images including a compressed image, in multiple planes, in a single frame, includes a compressed image decoder for decoding the compressed image, multiple arbiters for reading the decoded image data, and a decoder arbitration and semaphore control unit for splitting the compressed image into segments, assigning the segments to ones of the multiple planes, and allowing at least one arbiter to access the compressed image decoder to read the decoded data of the segment assigned to a plane mapped with the arbiter when the segment is being decoded.
摘要翻译：用于在单个帧中在多个平面中显示包括压缩图像的图像的多层显示系统包括用于对压缩图像进行解码的压缩图像解码器，用于读取解码图像数据的多个仲裁器，以及解码器仲裁和信号量控制单元，用于将压缩图像分割成段，将段分配给多个平面中的一个，并且允许至少一个仲裁器访问压缩图像解码器以读取分配给与仲裁器映射的平面的段的解码数据，当段正在解码。

2. 发明申请

US20160124889A1 ASYNCHRONOUS FIFO BUFFER WITH JOHNSON CODE WRITE POINTER 有权
标题翻译：具有约翰逊代码写入指针的异步FIFO缓冲区
公开(公告)号：US20160124889A1
公开(公告)日：2016-05-05
申请号：US14531992
申请日：2014-11-03
申请人： Chanpreet Singh , Kshitij Bajaj , Abhineet Kumar Bhojak , Anisha Ladsaria , Tejbal Prasad
发明人： Chanpreet Singh , Kshitij Bajaj , Abhineet Kumar Bhojak , Anisha Ladsaria , Tejbal Prasad
IPC分类号： G06F13/42 , G06F5/06 , G06F13/16
CPC分类号： G06F13/4239 , G06F5/065 , G06F5/14 , G06F13/1673 , G06F2205/067 , G06F2205/102
摘要： An asynchronous data transfer system includes a bus interface unit (BIU), a FIFO write logic module, a write pointer synchronizer, a write pointer validator, a FIFO read logic module, and an asynchronous FIFO buffer. The FIFO buffer receives a variable size data from the BIU and stores the variable size data at a write address. The FIFO write logic module generates a write pointer by encoding the write address using a Johnson code. The FIFO read logic module receives a synchronized write pointer at the asynchronous clock domain and generates a read address signal when the synchronized write pointer is a valid Johnson code format. The FIFO buffer transfers the variable size data to a processor based on the read address signal.
摘要翻译：异步数据传输系统包括总线接口单元（BIU），FIFO写逻辑模块，写指针同步器，写指针验证器，FIFO读逻辑模块和异步FIFO缓冲器。 FIFO缓冲器从BIU接收可变大小的数据，并将可变大小数据存储在写入地址。 FIFO写入逻辑模块通过使用Johnson代码对写入地址进行编码来生成写入指针。 FIFO读取逻辑模块在异步时钟域接收同步的写入指针，并且当同步的写入指针是有效的约翰逊码格式时，产生读取地址信号。 FIFO缓冲器基于读取的地址信号将可变大小的数据传送到处理器。

3. 发明申请

US20160247255A1 HEAD-UP DISPLAY WARPING CONTROLLER 有权
标题翻译：顶部显示器加热控制器
公开(公告)号：US20160247255A1
公开(公告)日：2016-08-25
申请号：US15024774
申请日：2013-09-27
申请人： Michael Andreas STAUDENMAIER , Kshitij BAJAJ , Chanpreet SINGH
发明人： Michael Andreas STAUDENMAIER , Kshitij BAJAJ , Chanpreet SINGH
IPC分类号： G06T3/00 , G02B27/01
CPC分类号： G06T3/0093 , G02B27/0025 , G02B27/01 , G02B27/0101 , G02B2027/011 , G02B2027/013 , G02B2027/014 , G06T3/005
摘要： A script-driven head-up display controller comprising an image warping unit and an image projection unit wherein the image warping unit is coupled to the image projection unit and is adapted to: receive a line-based warping descriptor comprising first information associated with a distortion caused by a non-flat display; and, in response to the reception of the line-based warping descriptor, the image warping unit is further adapted to, based on the line-based warping descriptor: fetch one or more lines of the source image; and, output to the image projection unit at least one output line of the output image associated with an electronic image warping of one or more pixels of the one or more input lines, and wherein the line-based warping descriptor further comprises second information associated with buffer management instructions calculated off-line.
摘要翻译：一种脚本驱动的平视显示控制器，包括图像扭曲单元和图像投影单元，其中图像扭曲单元耦合到图像投影单元，并适于：接收基于线的翘曲描述符，其包括与失真相关联的第一信息由非平面显示引起; 并且响应于所述基于行的翘曲描述符的接收，所述图像扭曲单元还适于基于所述基于线的翘曲描述符：获取所述源图像的一行或多行; 并且输出到与所述一个或多个输入线的一个或多个像素的电子图像变形相关联的所述输出图像的至少一个输出线，并且其中所述基于线的翘曲描述符还包括与所述一个或多个输入线相关联的第二信息缓冲管理指令离线计算。

4. 发明授权

US10026151B2 Head-up display warping controller 有权
公开(公告)号：US10026151B2
公开(公告)日：2018-07-17
申请号：US15024774
申请日：2013-09-27
申请人： Michael Andreas Staudenmaier , Kshitij Bajaj , Chanpreet Singh
发明人： Michael Andreas Staudenmaier , Kshitij Bajaj , Chanpreet Singh
IPC分类号： G06T3/00 , G02B27/00 , G02B27/01
摘要： A script-driven head-up display controller comprising an image warping unit and an image projection unit wherein the image warping unit is coupled to the image projection unit and is adapted to: receive a line-based warping descriptor comprising first information associated with a distortion caused by a non-flat display; and, in response to the reception of the line-based warping descriptor, the image warping unit is further adapted to, based on the line-based warping descriptor: fetch one or more lines of the source image; and, output to the image projection unit at least one output line of the output image associated with an electronic image warping of one or more pixels of the one or more input lines, and wherein the line-based warping descriptor further comprises second information associated with buffer management instructions calculated off-line.

5. 发明授权

US09710415B2 Asynchronous FIFO buffer with Johnson code write pointer 有权
公开(公告)号：US09710415B2
公开(公告)日：2017-07-18
申请号：US14531992
申请日：2014-11-03
申请人： Chanpreet Singh , Kshitij Bajaj , Abhineet Kumar Bhojak , Anisha Ladsaria , Tejbal Prasad
发明人： Chanpreet Singh , Kshitij Bajaj , Abhineet Kumar Bhojak , Anisha Ladsaria , Tejbal Prasad
IPC分类号： G06F13/26 , G06F13/42 , G06F13/16 , G06F5/06 , G06F5/14
CPC分类号： G06F13/4239 , G06F5/065 , G06F5/14 , G06F13/1673 , G06F2205/067 , G06F2205/102
摘要： An asynchronous data transfer system includes a bus interface unit (BIU), a FIFO write logic module, a write pointer synchronizer, a write pointer validator, a FIFO read logic module, and an asynchronous FIFO buffer. The FIFO buffer receives a variable size data from the BIU and stores the variable size data at a write address. The FIFO write logic module generates a write pointer by encoding the write address using a Johnson code. The FIFO read logic module receives a synchronized write pointer at the asynchronous clock domain and generates a read address signal when the synchronized write pointer is a valid Johnson code format. The FIFO buffer transfers the variable size data to a processor based on the read address signal.

6. 发明授权

US09484004B2 Display controller for display panel 有权
标题翻译：显示面板显示控制器
公开(公告)号：US09484004B2
公开(公告)日：2016-11-01
申请号：US14624529
申请日：2015-02-17
申请人： Chanpreet Singh , Kshitij Bajaj , Nakul Grover , Michael A. Staudenmaier
发明人： Chanpreet Singh , Kshitij Bajaj , Nakul Grover , Michael A. Staudenmaier
IPC分类号： G09G5/36 , G06T1/20 , G09G5/393 , G09G3/32 , G09G5/02 , G09G5/06
CPC分类号： G09G5/363 , G09G3/3208 , G09G5/026 , G09G5/06 , G09G5/393 , G09G2320/0693 , G09G2340/0457
摘要： A display controller includes first and second arbitrating units, a pixel data calculating unit, a latency measurement unit, and a clock divider. The first and second arbitrating units fetch first and second pixel data corresponding to at least one pixel from an external memory via a system bus. The pixel data calculating unit determines a size of the first and second pixel data. The latency measuring unit generates a first data rate value that is indicative of a latency of the system bus based on the size of the first and second pixel data. The clock divider receives a first clock signal modulation value corresponding to the first data rate value and alters a modulation of a reference clock signal. The graphics blending unit receives the first and second pixel data and provides blended pixel data to a display panel based on a modulated clock signal.
摘要翻译：显示控制器包括第一和第二仲裁单元，像素数据计算单元，等待时间测量单元和时钟分频器。第一和第二仲裁单元经由系统总线从外部存储器提取对应于至少一个像素的第一和第二像素数据。像素数据计算单元确定第一和第二像素数据的大小。延迟测量单元基于第一和第二像素数据的大小生成指示系统总线的等待时间的第一数据速率值。时钟分频器接收对应于第一数据速率值的第一时钟信号调制值，并改变参考时钟信号的调制。图形混合单元接收第一和第二像素数据，并且基于经调制的时钟信号将混合像素数据提供给显示面板。

7. 发明申请

US20160240172A1 DISPLAY CONTROLLER FOR DISPLAY PANEL 有权
标题翻译：显示面板显示控制器
公开(公告)号：US20160240172A1
公开(公告)日：2016-08-18
申请号：US14624529
申请日：2015-02-17
申请人： CHANPREET SINGH , Kshitij Bajaj , Nakul Grover , Michael A. Staudenmaier
发明人： CHANPREET SINGH , Kshitij Bajaj , Nakul Grover , Michael A. Staudenmaier
IPC分类号： G09G5/36 , G06T1/20 , G09G5/393
CPC分类号： G09G5/363 , G09G3/3208 , G09G5/026 , G09G5/06 , G09G5/393 , G09G2320/0693 , G09G2340/0457
摘要： A display controller includes first and second arbitrating units, a pixel data calculating unit, a latency measurement unit, and a clock divider. The first and second arbitrating units fetch first and second pixel data corresponding to at least one pixel from an external memory via a system bus. The pixel data calculating unit determines a size of the first and second pixel data. The latency measuring unit generates a first data rate value that is indicative of a latency of the system bus based on the size of the first and second pixel data. The clock divider receives a first clock signal modulation value corresponding to the first data rate value and alters a modulation of a reference clock signal. The graphics blending unit receives the first and second pixel data and provides blended pixel data to a display panel based on a modulated clock signal.
摘要翻译：显示控制器包括第一和第二仲裁单元，像素数据计算单元，等待时间测量单元和时钟分频器。第一和第二仲裁单元经由系统总线从外部存储器提取对应于至少一个像素的第一和第二像素数据。像素数据计算单元确定第一和第二像素数据的大小。延迟测量单元基于第一和第二像素数据的大小生成指示系统总线的等待时间的第一数据速率值。时钟分频器接收对应于第一数据速率值的第一时钟信号调制值，并改变参考时钟信号的调制。图形混合单元接收第一和第二像素数据，并且基于经调制的时钟信号将混合像素数据提供给显示面板。

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