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1. 发明授权

US08705307B2 Memory system with dynamic refreshing 有权
标题翻译：内存系统动态刷新
公开(公告)号：US08705307B2
公开(公告)日：2014-04-22
申请号：US13298587
申请日：2011-11-17
申请人： Joab D. Henderson , Hillery C. Hunter , Warren E. Maule , Jeffrey A. Stuecheli
发明人： Joab D. Henderson , Hillery C. Hunter , Warren E. Maule , Jeffrey A. Stuecheli
IPC分类号： G11C7/00
CPC分类号： G11C11/40611 , G11C2211/4061
摘要： An embodiment provided is a memory system with dynamic refreshing that includes a memory device with memory cells. The system also includes a refresh module in communication with the memory device and with a memory controller, the refresh module configured for receiving a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is responsive to at least one of a desired bandwidth characteristic and a desired latency characteristic.
摘要翻译：提供的实施例是具有动态刷新的存储器系统，其包括具有存储器单元的存储器件。该系统还包括与存储器设备和存储器控制器通信的刷新模块，该刷新模块被配置用于从存储器控制器接收刷新命令，并且响应于接收到所述存储器控制器来刷新存储器设备中的多个存储器单元刷新命令。响应于接收到刷新命令刷新的存储器单元的数量响应期望带宽特性和期望延迟特性中的至少一个。

2. 发明授权

US08691831B2 Heterocyclic aspartyl protease inhibitors 有权
标题翻译：杂环天门冬氨酰蛋白酶抑制剂
公开(公告)号：US08691831B2
公开(公告)日：2014-04-08
申请号：US13416140
申请日：2012-03-09
申请人： Zhaoning Zhu , Brian McKittrick , Zhong-Yue Sun , Yuanzan C. Ye , Johannes H. Voight , Corey O. Strickland , Elizabeth M. Smith , Andrew W. Stamford , William J. Greenlee , Robert D. Mazzola, Jr. , John P. Caldwell , Jared N. Cumming , Lingyan Wang , Yusheng Wu , Ulrich Iserloh , Xiaoxiang Liu , Tao Guo , Thuy X. E. Le , Kurt W. Saionz , Suresh D. Babu , Rachael C. Hunter , Michelle L. Morris , Huizhong Gu , Gang Qian , Dawit Tadesse , Ying Huang , Guoqing Li , Jianping Pan , Jeffrey A. Misiaszek , Gaifa Lai , Jingqi Duo , Chuanxing Qu , Yuefei Shao
发明人： Zhaoning Zhu , Brian McKittrick , Zhong-Yue Sun , Yuanzan C. Ye , Johannes H. Voight , Corey O. Strickland , Elizabeth M. Smith , Andrew W. Stamford , William J. Greenlee , Robert D. Mazzola, Jr. , John P. Caldwell , Jared N. Cumming , Lingyan Wang , Yusheng Wu , Ulrich Iserloh , Xiaoxiang Liu , Tao Guo , Thuy X. E. Le , Kurt W. Saionz , Suresh D. Babu , Rachael C. Hunter , Michelle L. Morris , Huizhong Gu , Gang Qian , Dawit Tadesse , Ying Huang , Guoqing Li , Jianping Pan , Jeffrey A. Misiaszek , Gaifa Lai , Jingqi Duo , Chuanxing Qu , Yuefei Shao
IPC分类号： A01N43/54 , A61K31/505
CPC分类号： C07D233/88 , A61K31/4168 , A61K31/4178 , C07D239/22 , C07D401/06 , C07D401/10 , C07D403/06 , C07D409/04 , C07D409/14 , C07D413/04 , C07D417/10 , C07D417/14 , C07D495/10
摘要： Disclosed are compounds of the formula I or a stereoisomer, tautomer, or pharmaceutically acceptable salt or solvate thereof, wherein each variable in Formula I are as defined in the specification; and pharmaceutical compositions comprising the compounds of formula I. Also disclosed are methods of inhibiting aspartyl protease, and in particular, the methods of treating cardiovascular diseases, cognitive and neurodegenerative diseases, and the methods of inhibiting of Human Immunodeficiency Virus, plasmepins, cathepsin D and protozoal enzymes. Also disclosed are methods of treating cognitive or neurodegenerative diseases using the compounds of formula I in combination with a cholinesterase inhibitor or a muscarinic m1 agonist or m2 antagonist.
摘要翻译：公开了式I化合物或其立体异构体，互变异构体或其药学上可接受的盐或溶剂化物，其中式I中的每个变量如说明书中所定义; 以及包含式I化合物的药物组合物。还公开了抑制天冬氨酰蛋白酶的方法，特别是治疗心血管疾病，认知和神经退行性疾病的方法，以及抑制人类免疫缺陷病毒，plasmepins，组织蛋白酶D和原生动物酶。还公开了使用式I化合物与胆碱酯酶抑制剂或毒蕈碱m1激动剂或m2拮抗剂组合治疗认知或神经变性疾病的方法。

3. 发明授权

US08683128B2 Memory bus write prioritization 有权
公开(公告)号：US08683128B2
公开(公告)日：2014-03-25
申请号：US12775511
申请日：2010-05-07
申请人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0888 , Y02D10/13
摘要： A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.

4. 发明授权

US08635401B2 Method and apparatus for performing refresh operations in high-density memories 失效
标题翻译：用于在高密度存储器中执行刷新操作的方法和装置
公开(公告)号：US08635401B2
公开(公告)日：2014-01-21
申请号：US13453328
申请日：2012-04-23
申请人： John S. Dodson , Benjiman L. Goodman , Hillery C. Hunter , Steven Powell , Jeffrey A. Stuecheli
发明人： John S. Dodson , Benjiman L. Goodman , Hillery C. Hunter , Steven Powell , Jeffrey A. Stuecheli
IPC分类号： G06F13/10
CPC分类号： G11C11/40603
摘要： A method for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.
摘要翻译：公开了一种执行刷新操作的方法。响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

5. 发明授权

US08615634B2 Coordinated writeback of dirty cachelines 有权
标题翻译：脏缓存行的协调回写
公开(公告)号：US08615634B2
公开(公告)日：2013-12-24
申请号：US13447445
申请日：2012-04-16
申请人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0817 , G06F12/0897 , Y02D10/13
摘要： A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.
摘要翻译：数据处理系统包括处理器核心和耦合到处理器核心的高速缓存存储器层级。高速缓存存储器层级包括至少一个上级高速缓存和最低级高速缓存。存储器控制器耦合到最低级缓存和系统存储器，并且包括物理写队列，存储器控制器从该物理写队列将数据写入系统存储器。存储器控制器启动对最低级高速缓存的访问以放置到物理写入队列中，所选择的高速缓存线具有空间局部性，其中数据存在于物理写入队列中。

6. 发明申请

US20130018066A1 HETEROCYCLIC ASPARTYL PROTEASE INHIBITORS 有权
公开(公告)号：US20130018066A1
公开(公告)日：2013-01-17
申请号：US13551315
申请日：2012-07-17
申请人： Zhaoning Zhu , Brian A. McKittrick , Zhong-Yue Sun , Yuanzan C. Ye , Johannes H. Voigt , Corey Strickland , Elizabeth M. Smith , Andrew Stamford , William J. Greenlee , Robert Mazzola , John Caldwell , Jared N. Cumming , Lingyan Wang , Yusheng Wu , Ulrich Iserloh , Tao Guo , Thuy X.H. Le , Kurt W. Saionz , Suresh D. Babu , Rachael C. Hunter , Michelle L. Morris , Huizhong Gu , Gang Qian , Dawit Tadesse
发明人： Zhaoning Zhu , Brian A. McKittrick , Zhong-Yue Sun , Yuanzan C. Ye , Johannes H. Voigt , Corey Strickland , Elizabeth M. Smith , Andrew Stamford , William J. Greenlee , Robert Mazzola , John Caldwell , Jared N. Cumming , Lingyan Wang , Yusheng Wu , Ulrich Iserloh , Tao Guo , Thuy X.H. Le , Kurt W. Saionz , Suresh D. Babu , Rachael C. Hunter , Michelle L. Morris , Huizhong Gu , Gang Qian , Dawit Tadesse
IPC分类号： A61K31/4245 , A61P9/00 , A61P25/00 , C07D413/10 , A61P31/18 , A61P33/02 , A61K31/505 , C07D271/07 , A61K31/4439 , A61P25/28
CPC分类号： C07D233/46 , C07D233/70 , C07D233/88 , C07D239/22 , C07D239/70 , C07D271/07 , C07D273/00 , C07D401/04 , C07D401/08 , C07D401/10 , C07D401/12 , C07D403/04 , C07D403/06 , C07D403/08 , C07D403/10 , C07D403/12 , C07D405/10 , C07D409/04 , C07D409/10 , C07D409/14 , C07D413/10 , C07D413/12 , C07D417/06
摘要： Disclosed are compounds of the formula I or a stereoisomer, tautomer, or pharmaceutically acceptable salt or solvate thereof, wherein W is a bond, —C(═S)—, —S(O)—, —S(O)2—, —C(═O)—, —O—, —C(R6)(R7)—, —N(R5)— or —C(═N(R5))—; X is —O—, —N(R5)— or —C(R6)(R7)—; provided that when X is —O—, U is not —O—, —S(O)—, —S(O)2—, —C(═O)— or —C(═NR5)—; U is a bond, —S(O)—, —S(O)2—, —C(O)—, —O—, —P(O)(OR15)—, —C(═NR5)—, —(C(R6)(R7))b— or —N(R5)—; wherein b is 1 or 2; provided that when W is —S(O)—, —S(O)2—, —O—, or —N(R5)—, U is not —S(O)—, —S(O)2—, —O—, or —N(R5)—; provided that when X is —N(R5)— and W is —S(O)—, —S(O)2—, —O—, or —N(R5)—, then U is not a bond; and R1, R2, R3, R4, R5, R6, and R7 are as defined in the specification; and pharmaceutical compositions comprising the compounds of formula I. Also disclosed is the method of inhibiting aspartyl protease, and in particular, the methods of treating cardiovascular diseases, cognitive and neurodegenerative diseases, and the methods of inhibiting of Human Immunodeficiency Virus, plasmepins, cathepsin D and protozoal enzymes. Also disclosed are methods of treating cognitive or neurodegenerative diseases using the compounds of formula I in combination with a cholinesterase inhibitor or a muscarinic m1 agonist or m2 antagonist.

7. 发明授权

US08309017B2 Off-gas heat recovery and particulate collection 有权
标题翻译：废气热回收和颗粒物收集
公开(公告)号：US08309017B2
公开(公告)日：2012-11-13
申请号：US12621474
申请日：2009-11-18
申请人： William C. Hunter
发明人： William C. Hunter
IPC分类号： B65H20/00
CPC分类号： C21B7/22 , C21C5/40 , C21C2100/06 , F27B1/10 , F27D17/004 , F27D17/008 , Y02P10/265 , Y02P10/283
摘要： An exhaust stream buffering system is described to temper a temperature profile and reduce a particulate load to permit heat recovery and cleaning. The buffering system may reduce the volatile temperature profile to even the temperature spikes, and produce a more even cyclical temperature profile. When used in steel making facilities, the buffered stream may also be augmented by blast furnace gases to provide additional energy for a heat recovery system.
摘要翻译：描述了排气流缓冲系统以调节温度曲线并减少颗粒负载以允许热回收和清洁。缓冲系统可以将挥发性温度分布降低到甚至温度峰值，并且产生更均匀的循环温度分布。当用于炼钢设备时，缓冲流还可以通过高炉气体来增加，为热回收系统提供额外的能量。

8. 发明申请

US20120203969A1 MEMORY BUS WRITE PRIORITIZATION 失效
标题翻译：内存总线写入优先
公开(公告)号：US20120203969A1
公开(公告)日：2012-08-09
申请号：US13447462
申请日：2012-04-16
申请人： DAVID M. DALY , BENJIMAN L. GOODMAN , HILLERY C. HUNTER , WILLIAM J. STARKE , JEFFREY A. STUECHELI
发明人： DAVID M. DALY , BENJIMAN L. GOODMAN , HILLERY C. HUNTER , WILLIAM J. STARKE , JEFFREY A. STUECHELI
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0888 , Y02D10/13
摘要： A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.
摘要翻译：数据处理系统包括包括最低级高速缓存，耦合到多级高速缓存层级的处理器核心以及耦合到最低级高速缓存和存储器系统存储器的存储器总线的存储器控制器的多级高速缓存层级。存储器控制器包括物理读取队列，其缓冲通过存储器总线从系统存储器读取的数据，以及物理写入队列，其通过存储器总线缓冲要写入系统存储器的数据。存储器控制器基于最低级高速缓冲存储器中的多个脏高速缓存线，对存储器总线上的读操作授予优先级。

9. 发明申请

US20120203968A1 COORDINATED WRITEBACK OF DIRTY CACHELINES 有权
标题翻译：协调写入的快速缓存
公开(公告)号：US20120203968A1
公开(公告)日：2012-08-09
申请号：US13447445
申请日：2012-04-16
申请人： David M. DALY , Benjiman L. GOODMAN , Hillery C. HUNTER , William J. STARKE , Jeffrey A. STUECHELI
发明人： David M. DALY , Benjiman L. GOODMAN , Hillery C. HUNTER , William J. STARKE , Jeffrey A. STUECHELI
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0817 , G06F12/0897 , Y02D10/13
摘要： A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.
摘要翻译：数据处理系统包括处理器核心和耦合到处理器核心的高速缓存存储器层级。高速缓存存储器层级包括至少一个上级高速缓存和最低级高速缓存。存储器控制器耦合到最低级缓存和系统存储器，并且包括物理写队列，存储器控制器从该物理写队列将数据写入系统存储器。存储器控制器启动对最低级高速缓存的访问以放置到物理写入队列中，所选择的高速缓存线具有空间局部性，其中数据存在于物理写入队列中。

10. 发明授权

US08045603B2 Method and a multi-carrier transceiver supporting dynamic switching between active application sets 有权
标题翻译：方法和支持主动应用程序集之间的动态切换的多载波收发器
公开(公告)号：US08045603B2
公开(公告)日：2011-10-25
申请号：US12859086
申请日：2010-08-18
申请人： Marcos C. Tzannes , Michael A. Tzannes , David C. Hunter , Richard W. Gross , Halil Padir
发明人： Marcos C. Tzannes , Michael A. Tzannes , David C. Hunter , Richard W. Gross , Halil Padir
IPC分类号： H04L5/16
CPC分类号： H04L47/803 , H04B1/38 , H04L1/0018 , H04L1/0025 , H04L1/0057 , H04L1/007 , H04L1/0071 , H04L1/0075 , H04L5/0007 , H04L5/0042 , H04L5/0053 , H04L5/0064 , H04L5/008 , H04L5/0087 , H04L5/0096 , H04L25/4915 , H04L27/2608 , H04L47/10 , H04L47/18 , H04L47/263 , H04L47/826 , H04L47/828 , H04M11/062
摘要： A transceiver and method for communicating over a communications channel having a plurality of subchannels are described. In particular, the transceiver is capable of dynamically switching between communicating data for a first active application set and communicating data for a second different active application set. An active application set is defined as the set of one or more active applications for which the transceiver is currently communicating data. As part of communicating data for the first active application set, the transceiver allocates the subchannels to the one or more applications in the first application set. The transmission requirements of the first active application set defines a first communication state of the transceiver. When the transceiver dynamically transitions to communicating data for the second different application set, the transceiver reallocates the subchannels to the one or more applications in the second different application set. The transmission requirements of the second different active application set defines a second communication state of the transceiver. In one embodiment the transceiver modifies the data rates of subchannels in the Bit Allocation Table according to the transmission requirements of the application whose data is being transmitted on the particular subchannel. In another embodiment, the transceiver is capable of dynamically switching from transmitting data for an Internet access application to transmitting data for a voice telephony application in addition to the Internet access application. In a further embodiment, the ABCD voice telephony signaling bits can be transmitted with either the data from the Internet access application or the data from the voice telephony application.
摘要翻译：描述了一种用于通过具有多个子信道的通信信道进行通信的收发器和方法。特别地，收发器能够在用于第一活动应用集的通信数据和用于第二不同活动应用集的通信数据之间动态切换。活动应用集被定义为收发器正在向其传送数据的一个或多个活动应用的集合。作为用于传送第一活动应用集的数据的一部分，收发器将子信道分配给第一应用集中的一个或多个应用。第一活动应用集合的传输要求定义了收发信机的第一通信状态。当收发机动态地转换到用于第二不同应用集的通信数据时，收发器将子信道重新分配给第二不同应用集中的一个或多个应用。第二不同活动应用集合的传输要求定义了收发信机的第二通信状态。在一个实施例中，收发器根据其数据正在特定子信道上发送的应用的传输要求来修改位分配表中的子信道的数据速率。在另一个实施例中，除了因特网接入应用之外，收发器能够从用于因特网接入应用的发送数据到语音电话应用的发送数据的动态切换。在另一实施例中，ABCD语音电话信令比特可以与来自因特网接入应用的数据或来自语音电话应用的数据一起发送。

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