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1. 发明授权

US07579643B2 Capacitor having high electrostatic capacity, integrated circuit device including the capacitor and method of fabricating the same 有权
标题翻译：具有高静电容量的电容器，包括该电容器的集成电路器件及其制造方法
公开(公告)号：US07579643B2
公开(公告)日：2009-08-25
申请号：US11706972
申请日：2007-02-16
申请人： Byung-jun Oh , Kyung-tae Lee , Yoon-hae Kim
发明人： Byung-jun Oh , Kyung-tae Lee , Yoon-hae Kim
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A capacitor may include a first electrode, a second electrode, a low dielectric layer, and/or a high dielectric layer. The first electrode may include at least one first electrode branch. The second electrode may face the first electrode and include at least one second electrode branch. The low dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may have a higher dielectric constant than the low dielectric layer.
摘要翻译：电容器可以包括第一电极，第二电极，低介电层和/或高电介质层。第一电极可以包括至少一个第一电极分支。第二电极可面向第一电极并且包括至少一个第二电极分支。低电介质层可以形成在第一电极分支和第二电极分支之间。高电介质层可以形成在第一电极分支和第二电极分支之间。高介电层可以具有比低介电层更高的介电常数。

2. 发明授权

US07679123B2 Integrated circuit devices including a capacitor 有权
标题翻译：集成电路器件包括电容器
公开(公告)号：US07679123B2
公开(公告)日：2010-03-16
申请号：US11684865
申请日：2007-03-12
申请人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
发明人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
IPC分类号： H01L29/94
CPC分类号： H01L21/76801 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L27/0688 , H01L27/10852 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.
摘要翻译：集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。介电层位于下电极层上，电容器的导电上电极层位于电介质层上。第一金属间电介质层在上电极层上。第一金属间电介质层包括延伸到上电极层的至少一个通孔。第一导电互连层位于第一金属间电介质层的至少一个通孔上。第二金属间介电层位于第一金属间电介质层上。第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

3. 发明授权

US07208791B2 Integrated circuit devices including a capacitor 有权
标题翻译：集成电路器件包括电容器
公开(公告)号：US07208791B2
公开(公告)日：2007-04-24
申请号：US11168126
申请日：2005-06-28
申请人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
发明人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
IPC分类号： H01L27/108
CPC分类号： H01L21/76801 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L27/0688 , H01L27/10852 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.
摘要翻译：集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。介电层位于下电极层上，电容器的导电上电极层位于电介质层上。第一金属间电介质层在上电极层上。第一金属间电介质层包括延伸到上电极层的至少一个通孔。第一导电互连层位于第一金属间电介质层的至少一个通孔上。第二金属间介电层位于第一金属间电介质层上。第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

4. 发明申请

US20060009065A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060009065A1
公开(公告)日：2006-01-12
申请号：US11174864
申请日：2005-07-05
申请人： Kyoung-Woo Lee , Hong-Jae Shin , Jeong-Hoon Ahn , Seung-Man Choi , Byung-Jun Oh , Yoon-Hae Kim
发明人： Kyoung-Woo Lee , Hong-Jae Shin , Jeong-Hoon Ahn , Seung-Man Choi , Byung-Jun Oh , Yoon-Hae Kim
IPC分类号： H01R4/24
CPC分类号： H01L23/5223 , H01L21/76808 , H01L21/76877 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.
摘要翻译：在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。沿着第一开口的内轮廓形成下电极。第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有阶梯部分的第一开口。在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。在电介质层上形成上电极。因此，抑制了下电极和上电极之间的漏电流。

5. 发明申请

US20050247968A1 Integrated circuit devices including a capacitor 有权
标题翻译：集成电路器件包括电容器
公开(公告)号：US20050247968A1
公开(公告)日：2005-11-10
申请号：US11168126
申请日：2005-06-28
申请人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
发明人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/00 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/108
CPC分类号： H01L21/76801 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L27/0688 , H01L27/10852 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.
摘要翻译：集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。介电层位于下电极层上，电容器的导电上电极层位于电介质层上。第一金属间电介质层在上电极层上。第一金属间电介质层包括延伸到上电极层的至少一个通孔。第一导电互连层位于第一金属间电介质层的至少一个通孔上。第二金属间介电层位于第一金属间电介质层上。第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

6. 发明授权

US06940114B2 Integrated circuit devices including a MIM capacitor 有权
标题翻译：集成电路器件包括MIM电容器
公开(公告)号：US06940114B2
公开(公告)日：2005-09-06
申请号：US10657490
申请日：2003-09-08
申请人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
发明人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/00 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/108
CPC分类号： H01L21/76801 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L27/0688 , H01L27/10852 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a Metal-Insulator-Metal (MIM) capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the MIM capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.
摘要翻译：集成电路器件包括在集成电路衬底上的集成电路衬底和金属 - 绝缘体 - 金属（MIM）电容器的导电下电极层。电介质层位于下电极层上，MIM电容器的导电上电极层位于电介质层上。第一金属间电介质层在上电极层上。第一金属间电介质层包括延伸到上电极层的至少一个通孔。第一导电互连层位于第一金属间电介质层的至少一个通孔上。第二金属间电介质层位于第一金属间电介质层上。第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

7. 发明授权

US07417302B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07417302B2
公开(公告)日：2008-08-26
申请号：US11174864
申请日：2005-07-05
申请人： Kyoung-Woo Lee , Hong-Jae Shin , Jeong-Hoon Ahn , Seung-Man Choi , Byung-Jun Oh , Yoon-Hae Kim
发明人： Kyoung-Woo Lee , Hong-Jae Shin , Jeong-Hoon Ahn , Seung-Man Choi , Byung-Jun Oh , Yoon-Hae Kim
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L21/76808 , H01L21/76877 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.
摘要翻译：在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。沿着第一开口的内轮廓形成下电极。第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有台阶部分的第一开口。在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。在电介质层上形成上电极。因此，抑制了下电极和上电极之间的漏电流。

8. 发明授权

US07183202B2 Method of forming metal wiring in a semiconductor device 有权
标题翻译：在半导体器件中形成金属布线的方法
公开(公告)号：US07183202B2
公开(公告)日：2007-02-27
申请号：US10989668
申请日：2004-11-17
申请人： Sang-Jin Lee , Kyung-Tae Lee , Byung-Jun Oh
发明人： Sang-Jin Lee , Kyung-Tae Lee , Byung-Jun Oh
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming metal wiring in a semiconductor device is disclosed. The method uses a dual damascene process in which a trench is formed prior to a via-hole.
摘要翻译：公开了一种在半导体器件中形成金属布线的方法。该方法使用双镶嵌工艺，其中在通孔之前形成沟槽。

9. 发明申请

US20070200159A1 Capacitor having high electrostatic capacity, integrated circuit device including the capacitor and method of fabricating the same 有权
标题翻译：具有高静电容量的电容器，包括电容器的集成电路器件及其制造方法
公开(公告)号：US20070200159A1
公开(公告)日：2007-08-30
申请号：US11706972
申请日：2007-02-16
申请人： Byung-jun Oh , Kyung-tae Lee , Yoon-hae Kim
发明人： Byung-jun Oh , Kyung-tae Lee , Yoon-hae Kim
IPC分类号： H01L29/94
CPC分类号： H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A capacitor may include a first electrode, a second electrode, a low dielectric layer, and/or a high dielectric layer. The first electrode may include at least one first electrode branch. The second electrode may face the first electrode and include at least one second electrode branch. The low dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may have a higher dielectric constant than the low dielectric layer.
摘要翻译：电容器可以包括第一电极，第二电极，低介电层和/或高电介质层。第一电极可以包括至少一个第一电极分支。第二电极可面向第一电极并且包括至少一个第二电极分支。低电介质层可以形成在第一电极分支和第二电极分支之间。高电介质层可以形成在第一电极分支和第二电极分支之间。高介电层可以具有比低介电层更高的介电常数。

10. 发明申请

US20070145452A1 Integrated Circuit Devices Including A Capacitor 有权
标题翻译：包括电容器的集成电路器件
公开(公告)号：US20070145452A1
公开(公告)日：2007-06-28
申请号：US11684865
申请日：2007-03-12
申请人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
发明人： Byung-jun Oh , Kyung-tae Lee , Mu-kyeng Jung
IPC分类号： H01L29/94
CPC分类号： H01L21/76801 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L27/0688 , H01L27/10852 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.
摘要翻译：集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。介电层位于下电极层上，电容器的导电上电极层位于电介质层上。第一金属间电介质层在上电极层上。第一金属间电介质层包括延伸到上电极层的至少一个通孔。第一导电互连层位于第一金属间电介质层的至少一个通孔上。第二金属间介电层位于第一金属间电介质层上。第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

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