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1. 发明授权

US08750505B2 Apparatus and method for controlling conversion of broadcasting program based on program protection information 失效
标题翻译：基于程序保护信息控制广播节目转换的装置和方法
公开(公告)号：US08750505B2
公开(公告)日：2014-06-10
申请号：US13125778
申请日：2009-10-21
申请人： Hyon-Gon Choo , Jeho Nam , Sangwoo Ahn , Jooyoung Lee , Moon-Kyun Oh , Jin-Woo Hong , Won-Sik Cheong , Sang-Kwon Shin , Keunsik Lee , Byung-Sun Kim , Hee-Young Jun , Sang-Gyou Lee , Sang-Jin Kim , Sung-Jun Ahn , Sung-Hwan Park , Jooho Song
发明人： Hyon-Gon Choo , Jeho Nam , Sangwoo Ahn , Jooyoung Lee , Moon-Kyun Oh , Jin-Woo Hong , Won-Sik Cheong , Sang-Kwon Shin , Keunsik Lee , Byung-Sun Kim , Hee-Young Jun , Sang-Gyou Lee , Sang-Jin Kim , Sung-Jun Ahn , Sung-Hwan Park , Jooho Song
IPC分类号： H04L9/00
CPC分类号： H04N5/913 , H04N9/8042 , H04N21/4334 , H04N21/4405 , H04N21/4623 , H04N21/4627 , H04N2005/91364
摘要： Provided are an apparatus and method for controlling program conversion according to program protection information. The method for controlling conversion of a broadcasting program includes: demultiplexing a broadcasting program into broadcasting program data and program protection information; encrypting the broadcasting program data based on distribution condition of the program protection information when recordation of the broadcasting program data is requested; and recording the encrypted broadcasting program data.
摘要翻译：提供了一种根据程序保护信息来控制程序转换的装置和方法。用于控制广播节目的转换的方法包括：将广播节目解复用为广播节目数据和节目保护信息; 在请求广播节目数据的记录时，基于节目保护信息的分配条件来加密广播节目数据; 并记录加密的广播节目数据。

2. 发明申请

US20130065060A1 GRAPHENE PAPER WHICH REDUCED GRAPHENE OXIDE LAYERS AND COATING LAYERS ARE STACKED IN SEQUENCE AND PREPARATION METHOD THEREOF 有权
标题翻译：减少石墨氧化物层和涂层的石墨纸按序列堆叠和制备方法
公开(公告)号：US20130065060A1
公开(公告)日：2013-03-14
申请号：US13469297
申请日：2012-05-11
申请人： Wonoh Lee , Jea Uk Lee , Jin-Woo Yi , Sang-Bok Lee , Jun-Hyung Byun , Byung-Sun Kim
发明人： Wonoh Lee , Jea Uk Lee , Jin-Woo Yi , Sang-Bok Lee , Jun-Hyung Byun , Byung-Sun Kim
IPC分类号： B32B9/04 , B28B1/14 , B82Y30/00 , B82Y40/00
CPC分类号： H01M4/622 , B32B9/04 , B82Y30/00 , B82Y40/00 , H01M4/133 , H01M4/366 , H01M4/587 , Y10T428/31536
摘要： The present disclosure relates to a graphene paper which reduced graphene oxide layers and coating layers are stacked in sequence. The graphene paper prepared according to a preparation method of the present invention has excellent electrical conductivity and mechanical properties, and can be economically prepared in large-sized graphene paper, therefore may be efficiently applied to various electrical devices such as thin-film electrodes, flexible electrodes, super capacitors, semiconductor insulating layer reinforcements and TFT semiconductor layer-electrodes, and the like.
摘要翻译：本发明涉及按顺序堆叠氧化石墨烯层和涂层的石墨烯纸。根据本发明的制备方法制备的石墨烯纸具有优异的导电性和机械性能，并且可以经济地制备在大尺寸的石墨烯纸中，因此可以有效地应用于各种电气装置，例如薄膜电极，柔性电极，超级电容器，半导体绝缘层加强件和TFT半导体层电极等。

3. 发明申请

US20120037971A1 NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20120037971A1
公开(公告)日：2012-02-16
申请号：US13181700
申请日：2011-07-13
申请人： Oh-Kyum Kwon , Tae-Jung Lee , Kyoung-Eun Uhn , Byung-Sun Kim
发明人： Oh-Kyum Kwon , Tae-Jung Lee , Kyoung-Eun Uhn , Byung-Sun Kim
IPC分类号： H01L29/78 , H01L27/06 , H01L29/94
CPC分类号： H01L29/78 , H01L27/11519 , H01L27/11521 , H01L27/11529 , H01L27/11558 , H01L29/94
摘要： A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.
摘要翻译：非易失性存储器件具有通过器件隔离层在衬底中限定的第一有源区和第二有源区，设置在第一有源区上并包括第一电极图的金属氧化物半导体场效应晶体管（MOSFET）金属氧化物硅（MOS）电容器，其设置在第二有源区并且包括第二电极图案，并且其中第一电极图案在MOSFET的沟道的宽度方向上比第一有源区域窄。

4. 发明授权

US07348241B2 Cell structure of EPROM device and method for fabricating the same 有权
标题翻译： EPROM器件的单元结构及其制造方法
公开(公告)号：US07348241B2
公开(公告)日：2008-03-25
申请号：US11384727
申请日：2006-03-20
申请人： Joon-hyung Lee , Byung-sun Kim , Tae-jung Lee
发明人： Joon-hyung Lee , Byung-sun Kim , Tae-jung Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/513 , H01L29/66825 , H01L29/7881
摘要： Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack. Thus, ultraviolet rays can penetrate through the window and easily erase charges of the programmed cell.
摘要翻译：提供EPROM器件的单元结构及其制造方法。电池结构包括栅极堆叠，其包括第一浮置栅极，包括氮化物层的绝缘图案和顺序地堆叠在半导体衬底上的控制栅极，并且包括用于暴露所述顶部表面或两个侧壁的窗口第一个浮动栅极位于控制栅极的两侧，使得第一个浮动栅极的电荷可以被紫外线消除。电池结构还包括浮栅晶体管，其包括形成在半导体衬底上的栅极绝缘层，形成在栅极绝缘层上并连接到栅堆叠中的第一浮栅的第二浮栅，以及源极 /漏极，其形成在半导体衬底中以便与第二浮栅对准。在电池结构中，窗口形成在栅堆叠的第一浮栅的顶表面或两个侧壁上。因此，紫外线可以穿过窗口并容易地擦除编程单元的电荷。

5. 发明申请

US20060138970A1 Stabilizer circuit for high-voltage discharge lamp 失效
标题翻译：稳压电路用于高压放电灯
公开(公告)号：US20060138970A1
公开(公告)日：2006-06-29
申请号：US11317708
申请日：2005-12-22
申请人： Byung-Sun Kim , Kyung-Soo Seok
发明人： Byung-Sun Kim , Kyung-Soo Seok
IPC分类号： H05B41/24
CPC分类号： H05B41/288 , Y10S315/04 , Y10S315/05
摘要： A stabilizer circuit for a high-voltage discharge lamp is provided. The stabilizer comprises an electromagnetic interference (EMI) filter; a rectifying unit; a power factor correction (PFC) circuit; a buck converter; a commutator; an igniter; a high-voltage discharge lamp; a current detector; a voltage detector; an igniter voltage controller for receiving the voltage output from the igniter and controlling the voltage when abnormality in the high-voltage discharge lamp occurs.
摘要翻译：提供了一种用于高压放电灯的稳定电路。稳定器包括电磁干扰（EMI）滤波器; 整流单元功率因数校正（PFC）电路; 降压转换器; 换向器点火器高压放电灯; 电流检测器; 电压检测器; 点火器电压控制器，用于接收从点火器输出的电压并且在高压放电灯中发生异常时控制电压。

6. 发明授权

US06995421B2 Cell structure of non-volatile memory device and method for fabricating the same 失效
公开(公告)号：US06995421B2
公开(公告)日：2006-02-07
申请号：US10621571
申请日：2003-07-18
申请人： Tae-Jung Lee , Byung-Sun Kim , Joon-Hyung Lee
发明人： Tae-Jung Lee , Byung-Sun Kim , Joon-Hyung Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.

7. 发明授权

US06703280B2 SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same 有权
标题翻译：用于消除SOI MOSFET中的浮体效应的SOI半导体集成电路及其制造方法
公开(公告)号：US06703280B2
公开(公告)日：2004-03-09
申请号：US10330404
申请日：2002-12-27
申请人： Young-Wug Kim , Byung-Sun Kim , Hee-Sung Kang , Young-Gun Ko , Sung-Bae Park , Min-Su Kim , Kwang-Il Kim
发明人： Young-Wug Kim , Byung-Sun Kim , Hee-Sung Kang , Young-Gun Ko , Sung-Bae Park , Min-Su Kim , Kwang-Il Kim
IPC分类号： H01L218244
CPC分类号： H01L29/78615
摘要： A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.
摘要翻译：提供了绝缘体上硅（SOI）集成电路和制造SOI集成电路的方法。在SOI衬底上形成至少一个隔离晶体管有源区和体线。晶体管有源区和体线被与SOI衬底的掩埋绝缘层接触的隔离层围绕。晶体管有源区的侧壁的一部分延伸到主体线。因此，晶体管有源区域通过主体延伸部电连接到主体线路。身体延伸部分覆盖有身体绝缘层。绝缘栅图案形成在晶体管有源区上方，栅极图案的一端与主体绝缘层重叠。

8. 发明授权

US06521959B2 SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same 有权
标题翻译：用于消除SOI MOSFET中的浮体效应的SOI半导体集成电路及其制造方法
公开(公告)号：US06521959B2
公开(公告)日：2003-02-18
申请号：US09782116
申请日：2001-02-13
申请人： Young-Wug Kim , Byung-Sun Kim , Hee-Sung Kang , Young-Gun Ko , Sung-Dae Park , Min-Su Kim , Kwang-Il Kim
发明人： Young-Wug Kim , Byung-Sun Kim , Hee-Sung Kang , Young-Gun Ko , Sung-Dae Park , Min-Su Kim , Kwang-Il Kim
IPC分类号： H01L2972
CPC分类号： H01L29/78615
摘要： A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.
摘要翻译：提供了绝缘体上硅（SOI）集成电路和制造SOI集成电路的方法。在SOI衬底上形成至少一个隔离晶体管有源区和体线。晶体管有源区和体线被与SOI衬底的掩埋绝缘层接触的隔离层围绕。晶体管有源区的侧壁的一部分延伸到主体线。因此，晶体管有源区域通过主体延伸部电连接到主体线路。身体延伸部分覆盖有身体绝缘层。绝缘栅图案形成在晶体管有源区上方，栅极图案的一端与主体绝缘层重叠。

9. 发明授权

US06407429B1 Semiconductor device having silicon on insulator and fabricating method therefor 有权
公开(公告)号：US06407429B1
公开(公告)日：2002-06-18
申请号：US09658099
申请日：2000-09-08
申请人： Young-Gun Ko , Byung-Sun Kim , Young-Wug Kim
发明人： Young-Gun Ko , Byung-Sun Kim , Young-Wug Kim
IPC分类号： H01L310392
CPC分类号： H01L27/1203 , H01L21/84
摘要： The present invention relates to an SOI semiconductor device and a method for fabricating an SOI semiconductor device, in which the portions formed with silicide layers are laterally restricted by spacers to a predetermined range in the diffusion regions to be used for diodes or well resistors. In this manner, it is possible to fix the length of distance between the sides of a silicide layer and a diffusion region, greater than that available in the prior art techniques, thereby minimizing power leakage at the sides of the diffusion regions. In the SOI semiconductor device thus constructed, the diffusion regions to be used for diodes (or well resistors) are constructed with spacers in a double junction structure of different density of impurity layers (for instance, a P− or N− layer respectively surrounds a P+ or N+ layer), in other words, only onto a high density of impurity layer, the P+ or N+ layer, or in a single junction structure in which the spacers restrict a range of space for forming the silicide layer in the diffusion region.

10. 发明授权

US09147881B2 Graphene paper which reduced graphene oxide layers and coating layers are stacked in sequence and preparation method thereof 有权
标题翻译：依次层叠石墨烯氧化物层和被覆层的石墨烯纸，其制备方法
公开(公告)号：US09147881B2
公开(公告)日：2015-09-29
申请号：US13469297
申请日：2012-05-11
申请人： Wonoh Lee , Jea Uk Lee , Jin-Woo Yi , Sang-Bok Lee , Jun-Hyung Byun , Byung-Sun Kim
发明人： Wonoh Lee , Jea Uk Lee , Jin-Woo Yi , Sang-Bok Lee , Jun-Hyung Byun , Byung-Sun Kim
IPC分类号： B32B9/04 , B28B1/14 , B82Y30/00 , B82Y40/00 , H01M4/62 , H01M4/133 , H01M4/36 , H01M4/587
CPC分类号： H01M4/622 , B32B9/04 , B82Y30/00 , B82Y40/00 , H01M4/133 , H01M4/366 , H01M4/587 , Y10T428/31536
摘要： The present disclosure relates to a graphene paper which reduced graphene oxide layers and coating layers are stacked in sequence. The graphene paper prepared according to a preparation method of the present invention has excellent electrical conductivity and mechanical properties, and can be economically prepared in large-sized graphene paper, therefore may be efficiently applied to various electrical devices such as thin-film electrodes, flexible electrodes, super capacitors, semiconductor insulating layer reinforcements and TFT semiconductor layer-electrodes, and the like.
摘要翻译：本发明涉及按顺序堆叠氧化石墨烯层和涂层的石墨烯纸。根据本发明的制备方法制备的石墨烯纸具有优异的导电性和机械性能，并且可以经济地制备在大尺寸的石墨烯纸中，因此可以有效地应用于各种电气装置，例如薄膜电极，柔性电极，超级电容器，半导体绝缘层加强件和TFT半导体层电极等。

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