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1. 发明申请

US20100167182A1 BACKSIDE PHASE GRATING MASK AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：背面相位掩模及其制造方法
公开(公告)号：US20100167182A1
公开(公告)日：2010-07-01
申请号：US12493075
申请日：2009-06-26
申请人： Sung Hyun OH , Byung Ho Nam
发明人： Sung Hyun OH , Byung Ho Nam
IPC分类号： G03F1/00
CPC分类号： G03F7/70158 , G03F1/50
摘要： A mask includes mask patterns formed over a frontside of a substrate and a phase grating formed over a backside of the substrate. The mask patterns correspond to a layout of diagonal patterns extending in a direction rotated toward a predetermined direction from an axis of a rectangular coordinate system. The phase grating extends in a direction parallel to the extending direction of the mask patterns. The phase grating includes first and second phase regions alternately arranged over the backside of the substrate with a phase difference of 180° therebetween. The first and second phase regions induce a phase interference that blocks a zero-order light of an exposure light incident to the substrate and allows a primary light to be incident to the mask patterns.
摘要翻译：掩模包括形成在衬底的前侧上的掩模图案和形成在衬底的背面上的相位光栅。掩模图案对应于沿着从矩形坐标系的轴线朝向预定方向旋转的方向延伸的对角图案的布局。相位光栅在与掩模图案的延伸方向平行的方向上延伸。相位光栅包括交替布置在衬底背面上的相位差为180°的第一和第二相区域。第一和第二相区域引起阻挡入射到衬底的曝光光的零级光并允许初级光入射到掩模图案的相位干涉。

2. 发明申请

US20080157386A1 Semiconductor Device Having Dummy Pattern and the Method for Fabricating the Same 有权
标题翻译：具有虚拟图案的半导体器件及其制造方法
公开(公告)号：US20080157386A1
公开(公告)日：2008-07-03
申请号：US11763182
申请日：2007-06-14
申请人： Byung Ho Nam
发明人： Byung Ho Nam
IPC分类号： H01L23/52 , H01L21/3205
CPC分类号： H01L21/76819 , H01L23/522 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate with a pattern region and a dummy region, an interlayer dielectric film arranged on the semiconductor substrate, a semiconductor layer pattern arranged on the interlayer dielectric film in the pattern region, a dummy pattern arranged on the interlayer dielectric film in the dummy region, a contact plug arranged inside the interlayer dielectric film, and the contact plug connecting the semiconductor layer pattern to the semiconductor substrate, and a dummy plug arranged inside the interlayer dielectric film, the dummy plug corresponding to the dummy pattern. A method for fabricating the semiconductor device includes forming these structures.
摘要翻译：半导体器件包括具有图案区域和虚设区域的半导体衬底，布置在半导体衬底上的层间电介质膜，布置在图案区域中的层间电介质膜上的半导体层图案，布置在层间电介质膜上的虚设图案在虚拟区域中，布置在层间电介质膜内部的接触插塞和将半导体层图案连接到半导体衬底的接触插塞和布置在层间电介质膜内部的虚拟插头，虚拟插头对应于虚设图案。制造半导体器件的方法包括形成这些结构。

3. 发明授权

US08486822B2 Semiconductor device having dummy pattern and the method for fabricating the same 有权
标题翻译：具有虚设图案的半导体器件及其制造方法
公开(公告)号：US08486822B2
公开(公告)日：2013-07-16
申请号：US13018358
申请日：2011-01-31
申请人： Byung Ho Nam
发明人： Byung Ho Nam
IPC分类号： H01L21/4763
CPC分类号： H01L21/76819 , H01L23/522 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A method for fabricating a semiconductor device includes forming an interlayer dielectric film on a semiconductor substrate including a pattern region and a dummy region, forming a photoresist pattern on the interlayer dielectric film such that the pattern region and the dummy region are partially exposed, etching the interlayer dielectric film exposed through the photoresist pattern as an etching mask to form a contact hole and a dummy contact hole, filling the contact hole and the dummy contact hole with a conductive material to form a contact plug and a dummy plug, depositing a semiconductor layer on the contact plug and the dummy plug, and subjecting the semiconductor layer to patterning to form a semiconductor layer pattern and a dummy pattern.
摘要翻译：一种制造半导体器件的方法包括在包括图案区域和虚拟区域的半导体衬底上形成层间电介质膜，在层间电介质膜上形成光致抗蚀剂图案，使得图案区域和虚拟区域部分地暴露，蚀刻层间绝缘膜通过光致抗蚀剂图案作为蚀刻掩模暴露以形成接触孔和虚拟接触孔，用导电材料填充接触孔和虚拟接触孔，以形成接触塞和虚拟插塞，沉积半导体层在接触插塞和虚拟插头上，并对半导体层进行构图以形成半导体层图案和虚设图案。

4. 发明授权

US07422830B2 Method for detecting failure of database patterns of photo mask 失效
标题翻译：检测防伪数据库图案的方法
公开(公告)号：US07422830B2
公开(公告)日：2008-09-09
申请号：US11084618
申请日：2005-03-17
申请人： Byung Ho Nam , Byoung Sub Nam
发明人： Byung Ho Nam , Byoung Sub Nam
IPC分类号： G03F1/00
CPC分类号： G03F1/36
摘要： A method for detecting failure of database patterns of a photo mask including designing the database patterns of the photo mask according to a design rule of a semiconductor element; performing optical proximity correction (OPC) of the designed database patterns; and detecting failure of the database patterns by obtaining a plurality of bias values based on at least two space widths according to each of line critical dimensions (CDs) of the designed database patterns and by detecting the shape of the pattern having the optimum bias value. The method applies different space widths to the patterns according to critical dimensions of lines of the patterns of the photo mask to preliminarily detect patterning failure varied according to illuminating systems, sub-films, and thicknesses of resist, and to correct failure of the patterns, such as collapse or bridges of the patterns, generated from the different lengths of patterns lines having the same critical dimension, using different bias values.
摘要翻译：一种用于检测光掩模的数据库图案的故障的方法，包括根据半导体元件的设计规则设计光掩模的数据库图案; 执行所设计的数据库模式的光学邻近校正（OPC）; 以及通过根据所设计的数据库模式的每个线性关键维度（CD），并且通过检测具有最佳偏好值的图案的形状，通过基于至少两个空间宽度获得多个偏置值来检测数据库模式的失败。该方法根据光掩模的图案的线的临界尺寸对图案应用不同的空间宽度，以初步检测根据照射系统，子膜和抗蚀剂厚度而变化的图案化故障，并且校正图案的失败，例如使用不同的偏置值从具有相同临界尺寸的不同长度的图案线产生的图案的折叠或桥接。

5. 发明授权

US5859439A Apparatus for aligning semiconductor wafer using mixed light with different wavelengths 失效
标题翻译：使用不同波长的混合光对准半导体晶片的装置
公开(公告)号：US5859439A
公开(公告)日：1999-01-12
申请号：US774680
申请日：1996-12-26
申请人： Byung-Ho Nam , Jae-Keun Jeong
发明人： Byung-Ho Nam , Jae-Keun Jeong
IPC分类号： G01B11/00 , G03F9/00 , H01L21/027 , G01N21/86
CPC分类号： G03F9/70
摘要： An alignment system of a lithography apparatus which is capable of obtaining an alignment mark without being influenced the height of the alignment mark and the thickness of the photoresist, includes a plurality of light sources emitting a light having each different wavelength, a plurality of beam splitters which reflects some portion of light emitted from the light source and transmits other portion of light and combines the reflected light to emit, a spacial filter for transmitting a light incident through the beam splitter, a first lens for condensing the light transmitted through the spacial filter, a wafer stage on an upper surface of which the wafer having a plurality of alignment marks to diffract a beam incident from the first lens is mounted, a second lens for condensing the light diffracted from the alignment mark on the wafer, a diffraction grating for diffracting the direction of the beam condensed in the second lens, a light collecting device for collecting the light reflected in the diffraction grating and converting the light into an electrical signal, and a control unit from controlling the wafer stage in accordance with the signal applied from the light collecting device.
摘要翻译：能够获得对准标记而不影响对准标记的高度和光致抗蚀剂的厚度的光刻设备的对准系统包括发射具有不同波长的光的多个光源，多个分束器其反射从光源发射的光的一部分并透射其他部分的光并组合反射光以发射用于透射通过分束器入射的光的空间滤光器，用于会聚透过空间滤光器的光的第一透镜安装有用于衍射从第一透镜入射的光束的多个对准标记的晶片的上表面的晶片台，用于会聚从晶片上的对准标记衍射的光的第二透镜，用于衍射在第二透镜中聚光的光束的方向，用于收集光反射的光收集装置在衍射光栅中形成并将光转换成电信号，以及控制单元，根据从光收集装置施加的信号控制晶片台。

6. 发明授权

US08748065B2 Reflection type blank masks, methods of fabricating the same, and methods of fabricating reflection type photo masks using the same 有权
标题翻译：反射型空白掩模，其制造方法以及使用其形成反射型光掩模的方法
公开(公告)号：US08748065B2
公开(公告)日：2014-06-10
申请号：US13614373
申请日：2012-09-13
申请人： Yong Dae Kim , Byung Ho Nam
发明人： Yong Dae Kim , Byung Ho Nam
IPC分类号： G03F1/42 , G03F1/24
CPC分类号： G03F1/42 , G03F1/24
摘要： Reflection type blank masks are provided. The blank mask includes a substrate, a reflection layer substantially on the substrate, at least one fiducial mark substantially on the reflection layer, an absorption layer substantially on the at least one fiducial mark and the reflection layer, and a resist layer substantially on the absorption layer.
摘要翻译：提供反射式空白面具。空白掩模包括基板，基本上在基板上的反射层，基本上在反射层上的至少一个基准标记，基本上在至少一个基准标记和反射层上的吸收层，以及基本上在吸收层上的抗蚀剂层层。

7. 发明申请

US20080079040A1 Transistor And Method For Manufacturing The Same 审中-公开
标题翻译：晶体管及其制造方法
公开(公告)号：US20080079040A1
公开(公告)日：2008-04-03
申请号：US11758496
申请日：2007-06-05
申请人： Byung Ho Nam
发明人： Byung Ho Nam
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/42376 , H01L21/823437 , H01L21/823456 , H01L21/823828 , H01L21/82385 , H01L29/66621 , H01L29/66636
摘要： A transistor includes a semiconductor substrate including an active region defined by a device isolation layer, gate lines disposed at specified intervals on the active region of the semiconductor substrate, and trenches of a valley structure etched to a specified depth in the semiconductor substrate in contact with end portions of the gate lines.
摘要翻译：晶体管包括半导体衬底，该半导体衬底包括由器件隔离层限定的有源区，以半导体衬底的有源区上指定的间隔设置的栅极线以及蚀刻到半导体衬底中指定深度的谷结构的沟槽，栅极线的端部。

8. 发明申请

US20130323629A1 REFLECTION TYPE BLANK MASKS, METHODS OF FABRICATING THE SAME, AND METHODS OF FABRICATING REFLECTION TYPE PHOTO MASKS USING THE SAME 有权
标题翻译：反射型空白掩模，其制造方法以及使用其制造反射型遮罩的方法
公开(公告)号：US20130323629A1
公开(公告)日：2013-12-05
申请号：US13614373
申请日：2012-09-13
申请人： Yong Dae KIM , Byung Ho Nam
发明人： Yong Dae KIM , Byung Ho Nam
IPC分类号： G03F1/24
CPC分类号： G03F1/42 , G03F1/24
摘要： Reflection type blank masks are provided. The blank mask includes a substrate, a reflection layer substantially on the substrate, at least one fiducial mark substantially on the reflection layer, an absorption layer substantially on the at least one fiducial mark and the reflection layer, and a resist layer substantially on the absorption layer.
摘要翻译：提供反射式空白面具。空白掩模包括基板，基本上在基板上的反射层，基本上在反射层上的至少一个基准标记，基本上在至少一个基准标记和反射层上的吸收层，以及基本上在吸收层上的抗蚀剂层层。

9. 发明授权

US08021805B2 Backside phase grating mask and method for manufacturing the same 有权
标题翻译：背面相位光栅掩模及其制造方法
公开(公告)号：US08021805B2
公开(公告)日：2011-09-20
申请号：US12493075
申请日：2009-06-26
申请人： Sung Hyun Oh , Byung Ho Nam
发明人： Sung Hyun Oh , Byung Ho Nam
IPC分类号： G03F1/00 , G03C5/00
CPC分类号： G03F7/70158 , G03F1/50
摘要： A mask includes mask patterns formed over a frontside of a substrate and a phase grating formed over a backside of the substrate. The mask patterns correspond to a layout of diagonal patterns extending in a direction rotated toward a predetermined direction from an axis of a rectangular coordinate system. The phase grating extends in a direction parallel to the extending direction of the mask patterns. The phase grating includes first and second phase regions alternately arranged over the backside of the substrate with a phase difference of 180° therebetween. The first and second phase regions induce a phase interference that blocks a zero-order light of an exposure light incident to the substrate and allows a primary light to be incident to the mask patterns.
摘要翻译：掩模包括形成在衬底的前侧上的掩模图案和形成在衬底的背面上的相位光栅。掩模图案对应于沿着从矩形坐标系的轴线朝向预定方向旋转的方向延伸的对角图案的布局。相位光栅在与掩模图案的延伸方向平行的方向上延伸。相位光栅包括交替布置在衬底背面上的相位差为180°的第一和第二相区域。第一和第二相区域引起阻挡入射到衬底的曝光光的零级光并允许初级光入射到掩模图案的相位干涉。

10. 发明申请

US20110212619A1 Semiconductor Device Having Dummy Pattern and the Method for Fabricating the Same 有权
标题翻译：具有虚拟图案的半导体器件及其制造方法
公开(公告)号：US20110212619A1
公开(公告)日：2011-09-01
申请号：US13018358
申请日：2011-01-31
申请人： Byung Ho Nam
发明人： Byung Ho Nam
IPC分类号： H01L21/283
CPC分类号： H01L21/76819 , H01L23/522 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A method for fabricating a semiconductor device includes forming an interlayer dielectric film on a semiconductor substrate including a pattern region and a dummy region, forming a photoresist pattern on the interlayer dielectric film such that the pattern region and the dummy region are partially exposed, etching the interlayer dielectric film exposed through the photoresist pattern as an etching mask to form a contact hole and a dummy contact hole, filling the contact hole and the dummy contact hole with a conductive material to form a contact plug and a dummy plug, depositing a semiconductor layer on the contact plug and the dummy plug, and subjecting the semiconductor layer to patterning to form a semiconductor layer pattern and a dummy pattern.
摘要翻译：一种制造半导体器件的方法包括在包括图案区域和虚拟区域的半导体衬底上形成层间电介质膜，在层间电介质膜上形成光致抗蚀剂图案，使得图案区域和虚拟区域部分地暴露，蚀刻层间绝缘膜通过光致抗蚀剂图案作为蚀刻掩模暴露以形成接触孔和虚拟接触孔，用导电材料填充接触孔和虚拟接触孔，以形成接触塞和虚拟插塞，沉积半导体层在接触插塞和虚拟插头上，并对半导体层进行构图以形成半导体层图案和虚设图案。

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