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1. 发明授权

US08788551B2 Random number generation using switching regulators 失效
标题翻译：使用开关调节器产生随机数
公开(公告)号：US08788551B2
公开(公告)日：2014-07-22
申请号：US13297009
申请日：2011-11-15
申请人： Bruce Douglas Buch , Jon David Trantham
发明人： Bruce Douglas Buch , Jon David Trantham
IPC分类号： G06F1/02
CPC分类号： G06F7/588
摘要： Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.
摘要翻译：使用与电路硬件相关的熵特性生成随机数。与一种方法一致，使用开关电压调节器电路来产生随机数。产生响应于开关稳压器电路的开关状态的数据。然后从生成的数据生成多位随机数。

2. 发明授权

US08737000B2 Gain control for latency testing 有权
标题翻译：增益控制延迟测试
公开(公告)号：US08737000B2
公开(公告)日：2014-05-27
申请号：US13550308
申请日：2012-07-16
申请人： Stefan Andrei Ionescu , Bruce Douglas Buch
发明人： Stefan Andrei Ionescu , Bruce Douglas Buch
IPC分类号： G11B5/09
CPC分类号： G11B5/09 , G11B5/02 , G11B5/746 , G11B20/10305 , G11B20/10481
摘要： Approaches for determining the timing latency of a communication path are described. Some embodiments involve a method for testing timing latency. A signal is driven on a first data path and is returned through a second data path through a loop back element. The timing latency of at least a portion of the communication path that includes the first data path and the second data path is tested using the signal returned on the second data path. The gain of the second data path is adjusted to a test value during the testing of the timing latency.
摘要翻译：描述用于确定通信路径的定时等待时间的方法。一些实施例涉及用于测试定时等待时间的方法。信号在第一数据路径上被驱动，并通过环路元件通过第二数据路径返回。使用在第二数据路径上返回的信号来测试包括第一数据路径和第二数据路径的通信路径的至少一部分的定时等待时间。在测试时间延迟期间，将第二数据路径的增益调整为测试值。

3. 发明申请

US20140016221A1 PIN-EFFICIENT READER BIAS ENABLE CONTROL 有权
标题翻译：引脚效率读取器偏置控制
公开(公告)号：US20140016221A1
公开(公告)日：2014-01-16
申请号：US13550296
申请日：2012-07-16
申请人： Bruce Douglas Buch , Stefan Andrei Ionescu
发明人： Bruce Douglas Buch , Stefan Andrei Ionescu
IPC分类号： G11B15/12 , G11B5/09
CPC分类号： G11B5/09 , G11B5/012 , G11B5/02 , G11B19/02
摘要： Systems and methods are included for determining a presence of an upcoming reading field during a write mode of a storage device, and initiating a read-while write (RWW) mode of the storage device in response to the sensed reading field. Initiating the RWW mode comprises warming up the reader circuitry, generating a signal in response to an end to the write operation, and activating reader bias current in response to the generated signal.
摘要翻译：包括用于在存储装置的写入模式期间确定即将到来的读取区域的存在以及响应于感测的读取区域启动存储设备的读取（RWW）模式的系统和方法。启动RWW模式包括预热读取器电路，响应于写入操作的结束产生信号，以及响应于产生的信号激活读取器偏置电流。

4. 发明申请

US20110252289A1 ADJUSTING STORAGE DEVICE PARAMETERS BASED ON RELIABILITY SENSING 审中-公开
标题翻译：基于可靠性检测调整存储设备参数
公开(公告)号：US20110252289A1
公开(公告)日：2011-10-13
申请号：US12756974
申请日：2010-04-08
申请人： Ara Patapoutian , Bruce Douglas Buch
发明人： Ara Patapoutian , Bruce Douglas Buch
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/353 , G06F11/1048 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/29 , H03M13/2957
摘要： In general, this disclosure is directed to techniques for adjusting storage device parameters based on reliability sensing. According to one aspect, a method includes retrieving a codeword from a plurality of data blocks within a storage device, wherein each of the data blocks stores a respective portion of the codeword, generating a detected value for a bit within a first portion of the codeword based on information related to a reliability of a data block associated with the first portion, and performing error correction on a second portion of the codeword based on the detected value for the bit within the first portion of the codeword. According to another aspect, a method includes obtaining information related to a reliability of a data block within a storage device, and adjusting a data capacity for the storage device based on the information related to the reliability of the data block.
摘要翻译：通常，本公开涉及基于可靠性感测来调整存储设备参数的技术。根据一个方面，一种方法包括从存储设备内的多个数据块检索码字，其中每个数据块存储码字的相应部分，为码字的第一部分内的比特生成检测值基于与第一部分相关联的数据块的可靠性的信息，并且基于码字的第一部分内的比特的检测值对码字的第二部分执行纠错。根据另一方面，一种方法包括获得与存储装置内的数据块的可靠性相关的信息，并且基于与数据块的可靠性相关的信息来调整存储装置的数据容量。

5. 发明授权

US07911724B2 Write synchronization phase calibration for storage media 有权
标题翻译：为存储介质写入同步相位校准
公开(公告)号：US07911724B2
公开(公告)日：2011-03-22
申请号：US12475001
申请日：2009-05-29
申请人： Bruce Douglas Buch , Mathew P. Vea
发明人： Bruce Douglas Buch , Mathew P. Vea
IPC分类号： G11B5/09
CPC分类号： G11B5/59655 , B82Y10/00 , G11B5/743 , G11B5/746 , G11B20/10009 , G11B20/10222 , G11B20/10425 , G11B20/10481 , G11B20/14 , G11B2005/0005 , G11B2020/1275 , G11B2220/2516
摘要： A technique is described for write synchronization phase calibration for storage media (e.g., bit patterned media). In one embodiment, a calibration write clock signal may be generated at a frequency offset from a nominal dot frequency of a bit patterned storage media. A periodic signal that was written to the media synchronous to the calibration write clock signal may then be read and mixed with a reference periodic signal at the nominal dot frequency to obtain a difference signal. This difference signal may be demodulated to determine a phase correction for write synchronization to the media.
摘要翻译：描述了用于存储介质（例如，位图形介质）的写入同步相位校准的技术。在一个实施例中，校准写时钟信号可以以与位图形存储介质的标称点频率偏移的频率产生。然后可以将与校准写入时钟信号同步的写入媒体的周期性信号读取并以标称点频率与参考周期信号混合，以获得差分信号。该差分信号可以被解调以确定用于与介质的写入同步的相位校正。

6. 发明授权

US07876517B2 Measurement of round trip latency in write and read paths 有权
标题翻译：测量写入和读取路径中的往返延迟
公开(公告)号：US07876517B2
公开(公告)日：2011-01-25
申请号：US12267234
申请日：2008-11-07
申请人： Bruce Douglas Buch , Mathew P. Vea , Jon Karsten Klarqvist
发明人： Bruce Douglas Buch , Mathew P. Vea , Jon Karsten Klarqvist
IPC分类号： G11B5/09
CPC分类号： G11B20/22 , G11B20/10009 , G11B20/10046 , G11B20/10194 , G11B20/10222 , G11B20/10481 , G11B2220/2516
摘要： A method and apparatus for measuring latency in a communication path is provided. The technique includes driving a signal such as a square wave on the communication path, such as a write path such that it travels around the write-read path, and sensing a returned signal at one end of the write-read path. A square wave signal corresponding to the square wave driven on the write path is delayed by a predetermined phase thus generating a delayed signal. The returned signal and the delayed signal are mixed, producing a mixed signal. The mixed signal is integrated to obtain an integrated output. The phase by which the delayed signal is shifted is successively adjusted. Returned signals are mixed with such delayed signals until the integrated output is equal to zero. The phase shift amount that results in a nulled integrated output, less a quarter cycle of the square wave, is equal to the round trip latency of the write-read path.
摘要翻译：提供了一种用于测量通信路径中的等待时间的方法和装置。该技术包括在通信路径上驱动诸如方波的信号，例如写入路径，使得其绕写入读取路径传播，并且感测读写路径的一端的返回信号。对应于在写入路径上驱动的方波的方波信号被延迟预定的相位，从而产生延迟的信号。返回信号和延迟信号混合，产生混合信号。混合信号被集成以获得集成输出。相继调整延迟信号移位的相位。返回的信号与这样的延迟信号混合，直到积分输出等于零。导致无效的积分输出的相移量少于方波的四分之一周期，等于写入读取路径的往返延迟。

7. 发明申请

US20100118428A1 INTERSPERSED PHASE-LOCKED LOOP FIELDS FOR DATA STORAGE MEDIA SYNCHRONIZATION 有权
标题翻译：用于数据存储媒体同步的互相锁相环路
公开(公告)号：US20100118428A1
公开(公告)日：2010-05-13
申请号：US12267305
申请日：2008-11-07
申请人： BRUCE DOUGLAS BUCH , MEHMET FATIH ERDEN , BARMESHWAR VIKRAMADITYA
发明人： BRUCE DOUGLAS BUCH , MEHMET FATIH ERDEN , BARMESHWAR VIKRAMADITYA
IPC分类号： G11B5/09
CPC分类号： G11B5/59616 , B82Y10/00 , G11B5/09 , G11B5/743
摘要： Techniques are described for providing media-referenced timing for operations on a data storage medium. In particular, Phase-Locked Loop (PLL) synchronization fields may be interspersed within data fields of the medium and may be read to obtain timing measurements. The PLL fields are illustratively pre-recorded at predetermined intervals on the medium and have a fixed number of dots of the bit patterned medium between the PLL fields. Phase and frequency of a write clock may be controlled based on the read PLL fields to translate the timing measurements from the PLL fields into phase and frequency corrections to synchronize the write clock to the data storage medium,
摘要翻译：描述技术来提供用于数据存储介质上的操作的媒体参考定时。特别地，锁相环（PLL）同步字段可以散布在介质的数据字段内，并且可以被读取以获得定时测量。说明性地在介质上以预定的间隔预先记录PLL场，并且在PLL场之间具有固定数量的位图案化介质的点。可以基于读取的PLL字段来控制写时钟的相位和频率，以将来自PLL字段的定时测量值转换为相位和频率校正，以将写入时钟同步到数据存储介质，

8. 发明申请

US20130124591A1 RANDOM NUMBER GENERATION USING SWITCHING REGULATORS 失效
标题翻译：使用切换调节器的随机数生成
公开(公告)号：US20130124591A1
公开(公告)日：2013-05-16
申请号：US13297009
申请日：2011-11-15
申请人： Bruce Douglas Buch , Jon David Trantham
发明人： Bruce Douglas Buch , Jon David Trantham
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.
摘要翻译：使用与电路硬件相关的熵特性生成随机数。与一种方法一致，使用开关电压调节器电路来产生随机数。产生响应于开关稳压器电路的开关状态的数据。然后从生成的数据生成多位随机数。

9. 发明授权

US07969676B2 Interspersed phase-locked loop fields for data storage media synchronization 有权
标题翻译：用于数据存储介质同步的散置锁相环域
公开(公告)号：US07969676B2
公开(公告)日：2011-06-28
申请号：US12267305
申请日：2008-11-07
申请人： Bruce Douglas Buch , Mehmet Fatih Erden , Barmeshwar Vikramaditya
发明人： Bruce Douglas Buch , Mehmet Fatih Erden , Barmeshwar Vikramaditya
IPC分类号： G11B27/36
CPC分类号： G11B5/59616 , B82Y10/00 , G11B5/09 , G11B5/743
摘要： Techniques are described for providing media-referenced timing for operations on a data storage medium. In particular, Phase-Locked Loop (PLL) synchronization fields may be interspersed within data fields of the medium and may be read to obtain timing measurements. The PLL fields are illustratively pre-recorded at predetermined intervals on the medium and have a fixed number of dots of the bit patterned medium between the PLL fields. Phase and frequency of a write clock may be controlled based on the read PLL fields to translate the timing measurements from the PLL fields into phase and frequency corrections to synchronize the write clock to the data storage medium.
摘要翻译：描述技术来提供用于数据存储介质上的操作的媒体参考定时。特别地，锁相环（PLL）同步字段可以散布在介质的数据字段内，并且可以被读取以获得定时测量。说明性地在介质上以预定的间隔预先记录PLL场，并且在PLL场之间具有固定数量的位图案化介质的点。可以基于读取的PLL字段来控制写时钟的相位和频率，以将来自PLL场的定时测量值转换为相位和频率校正，以将写入时钟同步到数据存储介质。

10. 发明申请

US20100118433A1 WRITE PRECOMPENSATION SYSTEM 审中-公开
标题翻译：写预认证系统
公开(公告)号：US20100118433A1
公开(公告)日：2010-05-13
申请号：US12266677
申请日：2008-11-07
申请人： Bruce Douglas Buch
发明人： Bruce Douglas Buch
IPC分类号： G11B21/02
CPC分类号： G11B5/02 , B82Y10/00 , G11B5/59616 , G11B5/743 , G11B5/746 , G11B5/82
摘要： A write precompensation system comprises a write precompensation processor that calculates time shift information for the timing of individual write current transitions at a write head to coincide with a media pattern under the write head and a write precompensation controller that shifts the individual write current transitions in accordance with the time shift information.
摘要翻译：一种写入预补偿系统，包括一个写入预补偿处理器，用于计算在写入头处的各个写入电流转换的定时的时间偏移信息，以与写入头下面的介质模式一致;以及写入预补偿控制器，与时间偏移信息。

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