专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06516295B1 Method and apparatus for emulating self-modifying code 有权
标题翻译：用于模拟自修改代码的方法和装置
公开(公告)号：US06516295B1
公开(公告)日：2003-02-04
申请号：US09345331
申请日：1999-06-30
申请人： George A. Mann , Bruce A. Noyes , Rene-Joseph Chevance
发明人： George A. Mann , Bruce A. Noyes , Rene-Joseph Chevance
IPC分类号： G06F9455
CPC分类号： G06F9/455
摘要： In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies whether the Target instruction has been translated into Host code, and if already translated, whether it is an entry point, middle, or last instruction in a block of code. When an emulator encounters a code tag indicating an entry point into a block of code, execution control is transferred to the corresponding Host code. Upon completion of the Host code block, execution control is returned to the emulator, with an indication of the next Target system instruction to execute. One code tag value is utilized to identify self-modified code. Another code tag value is utilized to indicate how often untranslated Target instructions have been interpreted in order to determine when to perform DOCT.
摘要翻译：在实现用于在主机系统上模拟目标系统指令的动态对象代码转换（DOCT）的数据处理系统中，每个目标系统指令具有相关联的索引/偏移字段和相关联的代码标签，用于标识目标指令是否已经被转换为主机代码，如果已经被翻译，是否是代码块中的入口点，中间或最后一条指令。当仿真器遇到指示进入代码块的入口点的代码标签时，执行控制被传送到相应的主机代码。主机代码块完成后，执行控制返回到仿真器，并指示执行下一个目标系统指令。一个代码标签值用于识别自修改代码。另一个代码标签值用于指示未经翻译的目标指令的解释频率，以便确定何时执行DOCT。

2. 发明授权

US06480845B1 Method and data processing system for emulating virtual memory working spaces 有权
标题翻译：用于模拟虚拟内存工作空间的方法和数据处理系统
公开(公告)号：US06480845B1
公开(公告)日：2002-11-12
申请号：US09594350
申请日：2000-06-14
申请人： David A. Egolf , Stefan R. Bohult , Bruce A. Noyes , Chad Farmer
发明人： David A. Egolf , Stefan R. Bohult , Bruce A. Noyes , Chad Farmer
IPC分类号： G06F1730
CPC分类号： G06F9/45537 , G06F12/0284 , G06F12/109 , Y10S707/99936
摘要： In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Virtual-to-real address translation of a Target system effective address to a Host system virtual addresses is performed by identifying a working space for the effective address, determining a working space base address for that working space, and then performing a linear translation multiplying the effective address by a constant and adding it to the working space base address to generate the host system virtual address.
摘要翻译：在主机计算机系统上的多处理器目标计算机系统的仿真中，主机虚拟内存地址被映射并用作目标虚拟内存地址。相应地设置目标虚拟内存控制表。通过识别有效地址的工作空间，确定该工作空间的工作空间基地址，然后执行线性转换，将目标系统有效地址的虚拟到实际地址转换到主机系统虚拟地址有效地址通过常数将其添加到工作空间基地址来生成主机系统的虚拟地址。

3. 发明授权

US06915405B2 Emulated target associative memory system with a multi-digit incrementable validity counter 有权
标题翻译：具有多位可递增有效性计数器的模拟目标关联存储器系统
公开(公告)号：US06915405B2
公开(公告)日：2005-07-05
申请号：US10309460
申请日：2002-12-04
申请人： Bruce A. Noyes
发明人： Bruce A. Noyes
IPC分类号： G06F9/455 , G06F12/10 , G06F12/00
CPC分类号： G06F9/45537 , G06F12/1027
摘要： A host computer system, including an addressable main memory storing data pages and a page table, emulates a target computer system which includes an emulated target central processing unit, an emulated target associative memory and an emulated target multi-digit incrementable validity counter. The target associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the target processor when access to a given page in main memory is sought. Each entry in the target associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. The target multi-digit counter stores a current validity count. When access to a data page is sought, comparisons are made: 1) between the high order virtual address component of the data page and the high order virtual address component read from the target associative memory entry; and 2) between the multi-digit validity count read from the target associative memory entry and the multi-digit current validity count in the target counter. If there is a full match, the real page address of the requested page is read from the target associative memory entry. If there is not a match, the page table is consulted to obtain the real address of the requested page, and the target associative memory is updated accordingly.
摘要翻译：包括存储数据页和页表的可寻址主存储器的主计算机系统模拟包括仿真目标中央处理单元，仿真目标关联存储器和仿真目标多位可递增有效性计数器的目标计算机系统。目标关联存储器在寻求对主存储器中的给定页面的访问时，根据由目标处理器发出的低阶虚拟地址组件来存储多个条目。目标关联存储器中的每个条目包括分别保存的字段：1）高阶虚拟地址分量; 2）真实页面地址; 和3）多位数有效性计数。目标多位计数器存储当前的有效性计数。当寻求对数据页的访问时，进行比较：1）数据页的高阶虚拟地址组件和从目标关联存储器条目读取的高阶虚拟地址组件之间; 和2）从目标关联存储器条目读取的多位数有效性计数与目标计数器中的多位数当前有效性计数之间。如果存在完全匹配，则从目标关联存储器条目读取所请求页面的真实页面地址。如果没有匹配，则查询页表以获得所请求页面的真实地址，并相应地更新目标关联存储器。

4. 发明授权

US06728846B2 Method and data processing system for performing atomic multiple word writes 有权
标题翻译：用于执行原子多字写入的方法和数据处理系统
公开(公告)号：US06728846B2
公开(公告)日：2004-04-27
申请号：US09746240
申请日：2000-12-22
申请人： Bruce A. Noyes
发明人： Bruce A. Noyes
IPC分类号： G06F1200
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/30174
摘要： Atomic multiple word writes are provided when emulating a target system that supports atomic multiple word writes on a host system that does not. For each except the last word to be written, a gate flag is read, tested, and locked when it is found unlocked. The words are then written to memory in reverse order, unlocking the gate flags as they are written. In a host system with a longer word size than the target system, the gate flags can be stored in otherwise unused bits in the host system words containing the target system words to be written.
摘要翻译：当在不支持原子多字写入的主机系统上模拟目标系统时，提供原子多字写入。对于除写入的最后一个字之外的每个字，当锁定被解锁时，门标志被读取，测试和锁定。然后将这些字以相反的顺序写入存储器，在写入时对门标志进行解锁。在具有比目标系统更长的字大小的主机系统中，门标志可以存储在主机系统字中的另外未使用的位中，其中包含要写入的目标系统字。

5. 发明授权

US06529862B1 Method and apparatus for dynamic management of translated code blocks in dynamic object code translation 有权
标题翻译：动态对象代码转换中动态管理翻译代码块的方法和装置
公开(公告)号：US06529862B1
公开(公告)日：2003-03-04
申请号：US09345146
申请日：1999-06-30
申请人： George A. Mann , Bruce A. Noyes , Rene-Joseph Chevance
发明人： George A. Mann , Bruce A. Noyes , Rene-Joseph Chevance
IPC分类号： G06F944
CPC分类号： G06F9/3808 , G06F9/45504
摘要： In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies whether the Target instruction has been translated into Host code, and if already translated, whether it is an entry point, middle, or last instruction in a block of code. When an emulator encounters a code tag indicating an entry point into a block of code, execution control is transferred to the corresponding Host code. Upon completion of the Host code block, execution control is returned to the emulator, with an indication of the next Target system instruction to execute. One code tag value is utilized to identify self-modified code. Another code tag value is utilized to indicate how often untranslated Target instructions have been interpreted in order to determine when to perform DOCT.
摘要翻译：在实现用于在主机系统上模拟目标系统指令的动态对象代码转换（DOCT）的数据处理系统中，每个目标系统指令具有相关联的索引/偏移字段和相关联的代码标签，用于标识目标指令是否已经被转换为主机代码，如果已经被翻译，是否是代码块中的入口点，中间或最后一条指令。当仿真器遇到指示进入代码块的入口点的代码标签时，执行控制被传送到相应的主机代码。主机代码块完成后，执行控制返回到仿真器，并指示执行下一个目标系统指令。一个代码标签值用于识别自修改代码。另一个代码标签值用于指示未经翻译的目标指令的解释频率，以便确定何时执行DOCT。

6. 发明授权

US06457171B1 Storage structure for dynamic management of translated code blocks in dynamic object code translation 有权
标题翻译：动态对象代码转换中动态管理翻译代码块的存储结构
公开(公告)号：US06457171B1
公开(公告)日：2002-09-24
申请号：US09340497
申请日：1999-06-30
申请人： George A. Mann , Bruce A. Noyes , Rene-Joseph Chevance
发明人： George A. Mann , Bruce A. Noyes , Rene-Joseph Chevance
IPC分类号： G06F945
CPC分类号： G06F9/45504
摘要： In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies whether the Target instruction has been translated into Host code, and if already translated, whether it is an entry point, middle, or last instruction in a block of code. When an emulator encounters a code tag indicating an entry point into a block of code, execution control is transferred to the corresponding Host code. Upon completion of the Host code block, execution control is returned to the emulator, with an indication of the next Target system instruction to execute. One code tag value is utilized to identify self-modified code. Another code tag value is utilized to indicate how often untranslated Target instructions have been interpreted in order to determine when to perform DOCT.
摘要翻译：在实现用于在主机系统上模拟目标系统指令的动态对象代码转换（DOCT）的数据处理系统中，每个目标系统指令具有相关联的索引/偏移字段和相关联的代码标签，用于标识目标指令是否已经被转换为主机代码，如果已经被翻译，是否是代码块中的入口点，中间或最后一条指令。当仿真器遇到指示进入代码块的入口点的代码标签时，执行控制被传送到相应的主机代码。主机代码块完成后，执行控制返回到仿真器，并指示执行下一个目标系统指令。一个代码标签值用于识别自修改代码。另一个代码标签值用于指示未经翻译的目标指令的解释时间，以便确定何时执行DOCT。

7. 发明授权

US06763328B1 Method and data processing system for emulating virtual memory utilizing threads 有权
标题翻译：利用线程仿真虚拟内存的方法和数据处理系统
公开(公告)号：US06763328B1
公开(公告)日：2004-07-13
申请号：US09594623
申请日：2000-06-15
申请人： David A. Egolf , Stefan R. Bohult , Bruce A. Noyes , Chad Farmer
发明人： David A. Egolf , Stefan R. Bohult , Bruce A. Noyes , Chad Farmer
IPC分类号： G06F9455
CPC分类号： G06F9/4843 , G06F9/45533 , G06F2009/45583
摘要： In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Each Target processor is mapped to a Host thread. When a page fault is detected by the Host operating system, it is checked to see if it belongs to the Target system, and if it does, the executing thread transfers its processor identity to a free thread, and then completes processing the page fault. Upon completion, it marks the processes that had been executing on that thread and processor as available for execution, then blocks until activated. Another thread, upon dispatching that process, wakes up the blocked thread and transfers its processor identity to that thread, which continues to execute the interrupted process.
摘要翻译：在主机计算机系统上的多处理器目标计算机系统的仿真中，主机虚拟内存地址被映射并用作目标虚拟内存地址。相应地设置目标虚拟内存控制表。每个Target处理器都映射到主机线程。当主机操作系统检测到页面错误时，检查它是否属于目标系统，如果是，则执行的线程将其处理器标识传送到空闲线程，然后完成处理页面错误。完成后，它标记在该线程和处理器上执行的可用于执行的进程，然后阻止直到激活。在调度该进程时，另一个线程唤醒阻塞的线程并将其处理器标识传送到该线程，该线程继续执行中断的进程。

8. 发明授权

US06446094B1 Data structure for emulating virtual memory working spaces 有权
标题翻译：用于模拟虚拟内存工作空间的数据结构
公开(公告)号：US06446094B1
公开(公告)日：2002-09-03
申请号：US09594940
申请日：2000-06-15
申请人： David A. Egolf , Stefan R. Bohult , Bruce A. Noyes , Chad Farmer
发明人： David A. Egolf , Stefan R. Bohult , Bruce A. Noyes , Chad Farmer
IPC分类号： G06F1730
CPC分类号： G06F9/45537 , G06F12/1036 , G06F12/109 , Y10S707/99936 , Y10S707/99957
摘要： In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Virtual-to-real address translation of a Target system effective address to a Host system virtual addresses is performed by identifying a working space for the effective address, selecting a working space base address data structure entry utilizing the corresponding working space number, determining a working space base address from that selected working space base address data structure entry, and then performing a linear translation multiplying the effective address by a constant and adding it to the working space base address to generate the host system virtual address. A corresponding working space limit entry can be utilized to bounds check the addresses generated.
摘要翻译：在主机计算机系统上的多处理器目标计算机系统的仿真中，主机虚拟内存地址被映射并用作目标虚拟内存地址。相应地设置目标虚拟内存控制表。通过识别有效地址的工作空间，利用相应的工作空间编号选择工作空间基地址数据结构条目，确定工作空间数目，确定目标系统有效地址到主机系统虚拟地址的虚拟到实际地址转换从所选择的工作空间基地址数据结构条目的空间基地址，然后执行线性转换，将有效地址乘以常数，并将其添加到工作空间基地址以生成主机系统虚拟地址。可以使用相应的工作空间限制条目来界定生成的地址。

9. 发明授权

US06938145B2 Associative memory system with a multi-digit incrementable validity counter 有权
标题翻译：具有多位可递增有效性计数器的关联存储器系统
公开(公告)号：US06938145B2
公开(公告)日：2005-08-30
申请号：US10309459
申请日：2002-12-04
申请人： Bruce A. Noyes , Russell W. Guenthner
发明人： Bruce A. Noyes , Russell W. Guenthner
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1027
摘要： A computer system includes a central processing unit, an addressable main memory storing data pages and a page table, and an associative memory. The associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the CPU's processor when access to a given page in main memory is sought. Each entry in the associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. An incrementable multi-digit counter in the CPU stores a current validity count. When access to a data page is sought, a comparator receives: 1) the high order virtual address component of the data page; 2) the high order virtual address component read from the associative memory entry; 3) the multi-digit validity count read from the associative memory entry; and 4) the multi-digit current validity count in the counter. If there is a full match, a switch issues the real page address read from the associative memory entry. If there is not a match, the page table is consulted to obtain the real address of the requested page, and the associative memory is updated accordingly.
摘要翻译：计算机系统包括中央处理单元，存储数据页和页表的可寻址主存储器和关联存储器。关联存储器根据当CPU处理器发出的低阶虚拟地址组件访问主存储器中的给定页面时存储多个条目。关联存储器中的每个条目包括分别保持：1）高阶虚拟地址分量的字段; 2）真实页面地址; 和3）多位数有效性计数。 CPU中可增量的多位计数器存储当前的有效性计数。当寻求访问数据页时，比较器接收：1）数据页的高阶虚拟地址分量; 2）从关联存储器条目读取的高阶虚拟地址组件; 3）从关联存储器条目读取的多位数有效性计数; 和4）计数器中的多位数的当前有效性计数。如果完全匹配，则交换机会发出从关联内存条目读取的真实页面地址。如果没有匹配，则查询页表以获得所请求页面的真实地址，并且相关联的存储器被相应地更新。

10. 发明授权

US06922666B2 Method and data processing system for performing atomic multiple word reads 有权
标题翻译：用于执行原子多重字读取的方法和数据处理系统
公开(公告)号：US06922666B2
公开(公告)日：2005-07-26
申请号：US09746792
申请日：2000-12-22
申请人： Bruce A. Noyes
发明人： Bruce A. Noyes
IPC分类号： G06F9/455
CPC分类号： G06F9/45554 , G06F9/45558 , G06F2009/45583
摘要： Atomic multiple word reads are provided when emulating a target system that supports atomic multiple word reads on a host system that does not. For each except the last word to be read, a gate flag is read using an advanced speculative load, and tested, until found unlocked. Check speculation instructions are utilized after the gate flag tests to verify that the corresponding cache lines have not been invalidated through a write by another processor since the speculative loads were issued. In a host system with a longer word size than the target system, the gate flags can be stored in otherwise unused bits in the host system words containing the target system words to be written.
摘要翻译：当在不支持原子多重字读取的主机系统上模拟目标系统时，提供了原子多字读取。除了要读取的最后一个字之外，还将使用高级推测负载读取门标志，并进行测试，直到找到解锁。在门标志测试之后，检查猜测指令是否被用于验证相应的高速缓存行是否已经由另一个处理器的写入而无效，因为发布了推测负载。在具有比目标系统更长的字大小的主机系统中，门标志可以存储在主机系统字中的另外未使用的位中，其中包含要写入的目标系统字。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式