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1. 发明授权

US06760865B2 Multiple level built-in self-test controller and method therefor 失效
标题翻译：多级内置自检控制器及其方法
公开(公告)号：US06760865B2
公开(公告)日：2004-07-06
申请号：US09859324
申请日：2001-05-16
申请人： James S. Ledford , Alex S. Yap , Robert A. Jensen , Brian E. Cook , Mark S. Aurora
发明人： James S. Ledford , Alex S. Yap , Robert A. Jensen , Brian E. Cook , Mark S. Aurora
IPC分类号： G06F1100
CPC分类号： G11C29/1201 , G06F13/1694 , G11C16/04 , G11C29/16 , G11C2029/0401
摘要： An integrated circuit has a Built-In Self-Test (BIST) controller (10) that has a sequencer (16) that provides test algorithm information for multiple memories (44, 46, 48, 50). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces (32, 34, 36, 38) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. This timing information is read prior to performing the test algorithm and is used in performing the test algorithm.
摘要翻译：集成电路具有内置自检（BIST）控制器（10），其具有为多个存储器（44,46,48,50）提供测试算法信息的定序器（16）。定序器识别要执行的测试算法，多个存储器接口（32,34,36,38）解释定序器的输出并在多个存储器上执行算法。多个存储器可以在类型，大小，数据宽度等方面是不同的或相同的。具有多个存储器接口提供了灵活性来为每个存储器定制测试算法，但是仍保持识别测试算法的单一来源的优点。由于存储器是非易失性的，关于测试算法的定时信息被存储在存储器中。在执行测试算法之前读取该定时信息，并用于执行测试算法。

2. 发明授权

US5872794A Flash EPROM control with embedded pulse timer and with built-in signature analysis 失效
标题翻译：闪存EPROM控制与嵌入式脉冲定时器和内置签名分析
公开(公告)号：US5872794A
公开(公告)日：1999-02-16
申请号：US967206
申请日：1997-10-29
申请人： Brian E. Cook , Jeffery T. Richardson , Yu-Ying Jackson Leung
发明人： Brian E. Cook , Jeffery T. Richardson , Yu-Ying Jackson Leung
IPC分类号： G11C29/20 , G11C29/40 , G01R31/28
CPC分类号： G11C29/40 , G11C29/20
摘要： Built-In-Logic-Block-Observation registers BILBO are coupled to the output of a Control-Read-Only-Memory CROM in the write-state-machine of a flash EPROM. The Built-In-Logic-Block-Observation registers BILBO include master/slave latches M/SL, shadow latches SHL, and other logic circuitry that enable the various modes of operation required for pulse timing and for signature analysis. During operation a pre-defined FLASH command sequence requests a Control-Read-Only-Memory CROM signature analysis that executes a set of instructions causing the Built-In-Logic-Block-Observation registers BILBO to be placed in the Multiple-Input-Signature-Register Mode and that steps through the Control-Read-Only-Memory CROM until all valid addresses have been evaluated. The resultant Control-Read-Only-Memory CROM signature is then scanned out and verified. The invention eliminates the need for a separate stand-alone Linear-Feedback-Shift-Register LFSR used for pulse timing. The contents of the Control-Read-Only-Memory CROM are verified without the necessity for time-consuming scanning-out of each word.
摘要翻译：内置逻辑块观测寄存器BILBO耦合到闪存EPROM的写状态机中的控制只读存储器CROM的输出。内置逻辑块观测寄存器BILBO包括主/从锁存器M / SL，阴影锁存器SHL和其他逻辑电路，可实现脉冲定时和签名分析所需的各种操作模式。在操作期间，预定义的FLASH命令序列请求执行一组指令的控制只读存储器CROM签名分析，使得内置逻辑块观测寄存器BILBO被放置在多输入签名 - 注册模式，并通过控制只读存储器CROM进行步骤，直到所有有效地址已被评估为止。然后扫描出结果并验证所得到的控制只读存储器CROM签名。本发明消除了对用于脉冲定时的独立线性反馈移位寄存器LFSR的需要。验证控制只读存储器CROM的内容，而不需要耗费每个字的扫描。

3. 发明授权

US4887144A Topside substrate contact in a trenched semiconductor structure and method of fabrication 失效
标题翻译：沟槽半导体结构中的顶部衬底接触和制造方法
公开(公告)号：US4887144A
公开(公告)日：1989-12-12
申请号：US21568
申请日：1987-02-27
申请人： Brian E. Cook , Ralph S. Keen
发明人： Brian E. Cook , Ralph S. Keen
IPC分类号： H01L21/74 , H01L21/762 , H01L29/10 , H01L29/45 , H01L29/732
CPC分类号： H01L29/10 , H01L21/743 , H01L21/76202 , H01L21/76224 , H01L21/76294 , H01L29/456 , H01L29/7322
摘要： A process for forming a topside substrate contact in a trenched semiconductor structure. A trench (24, 26) is etched into a P- block of substrate (10) material. The trench (24, 26) is filled with silicon dioxide, and then the substrate material (10) circumscribed by the trench (24, 26) is removed to form a well. A subcollector (48) is implanted in the well of the P. substrate. Epi material (50) is grown in the well to the top of the silicon dioxide-filled trench. A device (59) is formed in the epi (50). Ohmic contacts (70) are formed on the topside of the substrate to the device (59) within the well, and to the P- substrate itself outside the trench.
摘要翻译：一种用于在沟槽半导体结构中形成顶层衬底接触的工艺。将沟槽（24,26）蚀刻到衬底（10）材料的P块中。沟槽（24,26）填充有二氧化硅，然后去除由沟槽（24,26）限定的衬底材料（10）以形成阱。将子集电极（48）植入到P.基板的孔中。 Epi材料（50）在井中生长到填充二氧化硅的沟槽的顶部。装置（59）形成在外壳（50）中。欧姆接触件（70）形成在衬底的顶部到阱内的器件（59），以及在沟槽外部的P-衬底本身。

4. 发明授权

US06347056B1 Recording of result information in a built-in self-test circuit and method therefor 有权
标题翻译：在内置的自检电路中记录结果信息及其方法
公开(公告)号：US06347056B1
公开(公告)日：2002-02-12
申请号：US09859333
申请日：2001-05-16
申请人： James S. Ledford , Alex S. Yap , Brian E. Cook
发明人： James S. Ledford , Alex S. Yap , Brian E. Cook
IPC分类号： G11C700
CPC分类号： G11C29/44
摘要： An integrated circuit has a Built-In Self-Test (BIST) controller (10) that has a sequencer (16) that provides test algorithm information for multiple memories (44, 46, 48, 50). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces (32, 34, 36, 38) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. When test algorithms fail or complete execution, pertinent BIST information is stored in non-user addressable space of the multiple memories.
摘要翻译：集成电路具有内置自检（BIST）控制器（10），其具有为多个存储器（44,46,48,50）提供测试算法信息的定序器（16）。定序器识别要执行的测试算法，多个存储器接口（32,34,36,38）解释定序器的输出并在多个存储器上执行算法。多个存储器可以在类型，大小，数据宽度等方面是不同的或相同的。具有多个存储器接口提供了灵活性来为每个存储器定制测试算法，但是仍保持识别测试算法的单一来源的优点。由于存储器是非易失性的，关于测试算法的定时信息被存储在存储器中。当测试算法失败或完成执行时，相关BIST信息存储在多个存储器的非用户可寻址空间中。

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