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1. 发明申请

US20050272245A1 Method for forming contact plug of semiconductor device 有权
标题翻译：形成半导体器件接触插塞的方法
公开(公告)号：US20050272245A1
公开(公告)日：2005-12-08
申请号：US11026226
申请日：2004-12-28
申请人： Bong-Ho Choi , Ik-Soo Choi
发明人： Bong-Ho Choi , Ik-Soo Choi
IPC分类号： H01L21/28 , H01L21/02 , H01L21/311 , H01L21/321 , H01L21/3213 , H01L21/4763 , H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/02063 , H01L21/31116 , H01L21/31144 , H01L21/32115 , H01L21/32137 , H01L21/7684
摘要： Disclosed is a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a plurality of contact plugs capable of preventing a self-aligned contact (SAC) fail during forming a plurality of contact holes formed by using a SAC etching process and a defect generation during performing a plug isolation process. The present invention prevents a Pinocchio defect that is a fundamental problem caused by the chemical mechanical polishing (CMP) process and simplifies a subsequent cleaning process performed according to the particles. Accordingly, it is possible to develop products with a high quality and a high speed and to replace the CMP process having a high unit process cost with an etch back process, thereby providing an effect of increasing a price competitiveness.
摘要翻译：公开了一种制造半导体器件的方法; 更具体地，涉及一种制造多个接触塞的方法，其能够在形成通过使用SAC蚀刻工艺形成的多个接触孔和在执行插塞隔离处理期间的缺陷产生时防止自对准接触（SAC）失效。本发明防止作为由化学机械抛光（CMP）工艺引起的根本问题的皮诺the（Pinocchio）缺陷，并简化了根据颗粒进行的随后的清洗处理。因此，可以开发具有高质量和高速度的产品，并且通过回蚀工艺替代具有高单位加工成本的CMP工艺，从而提供提高价格竞争力的效果。

2. 发明授权

US08786047B2 Semiconductor device with isolation layer, electronic device having the same, and method for fabricating the same 有权
标题翻译：具有隔离层的半导体器件，具有该隔离层的电子器件及其制造方法
公开(公告)号：US08786047B2
公开(公告)日：2014-07-22
申请号：US13544411
申请日：2012-07-09
申请人： Hyung-Hwan Kim , Bong-Ho Choi , Jin-Yul Lee , Seung-Seok Pyo
发明人： Hyung-Hwan Kim , Bong-Ho Choi , Jin-Yul Lee , Seung-Seok Pyo
IPC分类号： H01L21/70 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/762 , H01L21/76229 , H01L27/10894
摘要： A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
摘要翻译：埋置在沟槽中的具有隔离层的半导体器件包括形成在沟槽表面上的界面层，形成在沟槽底部拐角处的界面层中的缓冲层，形成在界面层上的衬层，以及间隙填充层间隙填充衬里层上的沟槽。沟槽包括形成在其底角处的微沟槽，并且缓冲层填充微沟槽。

3. 发明授权

US07314825B2 Method for forming contact plug of semiconductor device 有权
标题翻译：形成半导体器件接触插塞的方法
公开(公告)号：US07314825B2
公开(公告)日：2008-01-01
申请号：US11026226
申请日：2004-12-28
申请人： Bong-Ho Choi , Ik-Soo Choi
发明人： Bong-Ho Choi , Ik-Soo Choi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/02063 , H01L21/31116 , H01L21/31144 , H01L21/32115 , H01L21/32137 , H01L21/7684
摘要： Disclosed is a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a plurality of contact plugs capable of preventing a self-aligned contact (SAC) fail during forming a plurality of contact holes formed by using a SAC etching process and a defect generation during performing a plug isolation process. The present invention prevents a Pinocchio defect that is a fundamental problem caused by the chemical mechanical polishing (CMP) process and simplifies a subsequent cleaning process performed according to the particles. Accordingly, it is possible to develop products with a high quality and a high speed and to replace the CMP process having a high unit process cost with an etch back process, thereby providing an effect of increasing a price competitiveness.
摘要翻译：公开了一种制造半导体器件的方法; 更具体地，涉及一种制造多个接触塞的方法，其能够在形成通过使用SAC蚀刻工艺形成的多个接触孔和在执行插塞隔离处理期间的缺陷产生时防止自对准接触（SAC）失效。本发明防止作为由化学机械抛光（CMP）工艺引起的根本问题的皮诺the（Pinocchio）缺陷，并简化了根据颗粒进行的随后的清洗处理。因此，可以开发具有高质量和高速度的产品，并且通过回蚀工艺替代具有高单位加工成本的CMP工艺，从而提供提高价格竞争力的效果。

4. 发明申请

US20100159683A1 Method for Fabricating Semiconductor Device Having Recess Channel 审中-公开
标题翻译：制造具有凹陷通道的半导体器件的方法
公开(公告)号：US20100159683A1
公开(公告)日：2010-06-24
申请号：US12494055
申请日：2009-06-29
申请人： Jin Yul Lee , Bong Ho Choi , Kwang Kee Chae , Dong Seok Kim , Jae Seon Yu , Hyung Hwan Kim , Jae Kyun Lee
发明人： Jin Yul Lee , Bong Ho Choi , Kwang Kee Chae , Dong Seok Kim , Jae Seon Yu , Hyung Hwan Kim , Jae Kyun Lee
IPC分类号： H01L21/28 , H01L21/306
CPC分类号： H01L21/3185 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28123 , H01L21/3065 , H01L21/3086 , H01L21/3141 , H01L21/76232 , H01L29/1037 , H01L29/66621
摘要： A method for fabricating a semiconductor device having a recess channel includes forming an isolation layer that delimits an active region over a semiconductor substrate; exposing a region to be formed with a bulb recess trench over the semiconductor substrate; forming an upper trench by etching the exposed portion of the semiconductor substrate; forming, on a side wall of the upper trench, a silicon nitride barrier layer that exposes a bottom face of the upper trench but blocks a side wall of the upper trench; forming a lower trench of a bulb type by etching the exposed bottom face of the upper trench using the etch barrier layer as an etch mask, to form the bulb recess trench including the upper trench and the lower trench; forming a fin-structured bottom protrusion part including an upper face and a side face by etching the isolation layer so that the isolation layer has a surface lower than the bottom face of the lower trench; and forming a gate stack overlapped with the bulb recess trench and the bottom protrusion part.
摘要翻译：一种制造具有凹槽通道的半导体器件的方法包括：形成限定半导体衬底上的有源区的隔离层; 在半导体衬底上露出要形成有灯泡凹槽的区域; 通过蚀刻半导体衬底的暴露部分形成上沟槽; 在所述上沟槽的侧壁上形成暴露所述上沟槽的底面但阻挡所述上沟槽的侧壁的氮化硅阻挡层; 通过使用蚀刻阻挡层作为蚀刻掩模蚀刻上沟槽的暴露的底面来形成灯泡类型的下沟槽，以形成包括上沟槽和下沟槽的灯泡凹槽; 通过蚀刻隔离层形成包括上表面和侧面的翅片结构的底部突出部分，使得隔离层具有比下沟槽的底面低的表面; 以及形成与灯泡凹槽和底部突出部重叠的栅极叠层。

5. 发明授权

US07160814B2 Method for forming contact in semiconductor device 失效
标题翻译：在半导体器件中形成接触的方法
公开(公告)号：US07160814B2
公开(公告)日：2007-01-09
申请号：US10882698
申请日：2004-06-29
申请人： Chang-Youn Hwang , Bong-Ho Choi , Jung-Geun Kim
发明人： Chang-Youn Hwang , Bong-Ho Choi , Jung-Geun Kim
IPC分类号： H01L21/461
CPC分类号： H01L21/76897 , H01L21/02052 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L21/76801 , H01L21/76802 , H01L21/76831
摘要： Disclosed is a method for forming a contact in a semiconductor device. The method includes the steps of: forming a bit line on a substrate; forming an oxide layer made of high density plasma (HDP) oxide on a substrate structure including the bit line and the substrate; forming a hard mask on the oxide layer; and performing an etching process for forming a storage node contact, wherein the etching process is performed after the bit line, the oxide layer and the hard mask are formed with a predetermined thickness and a predetermined tensile stress such that a total compressive stress value of the bit line, the oxide layer and the hard mask layer is less than a critical value of a lifting phenomenon.
摘要翻译：公开了一种在半导体器件中形成接触的方法。该方法包括以下步骤：在衬底上形成位线; 在包括所述位线和所述衬底的衬底结构上形成由高密度等离子体（HDP）氧化物制成的氧化物层; 在氧化物层上形成硬掩模; 以及进行用于形成存储节点接触的蚀刻工艺，其中在所述位线，所述氧化物层和所述硬掩模形成预定厚度和预定拉伸应力之后执行所述蚀刻工艺，使得所述蚀刻工艺的总压缩应力值位线，氧化物层和硬掩模层小于提升现象的临界值。

6. 发明授权

US06169657A Radiating device for electronic appliances 有权
标题翻译：电子电器用散热装置
公开(公告)号：US06169657A
公开(公告)日：2001-01-02
申请号：US09196552
申请日：1998-11-20
申请人： Kyeong-Sik Choi , Bong-Ho Choi
发明人： Kyeong-Sik Choi , Bong-Ho Choi
IPC分类号： H05K720
CPC分类号： H01L23/3672 , H01L2924/0002 , H01L2924/00
摘要： A radiating device for an electronic appliance is provided with a plurality of embossed portions at surfaces thereof and vents in the embossed portions, portions thereof which are not embossed or the embossed portions and the portions thereof which are not embossed. Thus, the radiating device according to the present invention protects other components of the electronic appliance which are not strong enough to endure heat by rapidly radiating the heat generated from a transistor or an integrated circuit.
摘要翻译：一种用于电子设备的辐射装置在其表面设置有多个压花部分，并且在压纹部分中的通风孔，其未被压花的部分或不压花的压花部分及其部分。因此，根据本发明的辐射装置通过快速辐射从晶体管或集成电路产生的热来保护电子设备的其它部件不够强大以承受热量。

7. 发明申请

US20130249048A1 SEMICONDUCTOR DEVICE WITH ISOLATION LAYER, ELECTRONIC DEVICE HAVING THE SAME, AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有隔离层的半导体器件，具有该隔离层的电子器件及其制造方法
公开(公告)号：US20130249048A1
公开(公告)日：2013-09-26
申请号：US13544411
申请日：2012-07-09
申请人： Hyung-Hwan KIM , Bong-Ho CHOI , Jin-Yul LEE , Seung-Seok PYO
发明人： Hyung-Hwan KIM , Bong-Ho CHOI , Jin-Yul LEE , Seung-Seok PYO
IPC分类号： H01L27/04 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/762 , H01L21/76229 , H01L27/10894
摘要： A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
摘要翻译：埋置在沟槽中的具有隔离层的半导体器件包括形成在沟槽表面上的界面层，形成在沟槽底部拐角处的界面层中的缓冲层，形成在界面层上的衬层，以及间隙填充层间隙填充衬里层上的沟槽。沟槽包括形成在其底角处的微沟槽，并且缓冲层填充微沟槽。

8. 发明授权

US06566188B2 Method of forming contact holes in semiconductor devices and method of forming capacitors using the same 有权
公开(公告)号：US06566188B2
公开(公告)日：2003-05-20
申请号：US10177950
申请日：2002-06-21
申请人： Dong Hyun Kim , Bong Ho Choi , Yong Tae Cho
发明人： Dong Hyun Kim , Bong Ho Choi , Yong Tae Cho
IPC分类号： H01L218242
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/76802 , H01L21/76805 , H01L21/76814 , H01L27/10855 , H01L28/91
摘要： A method of manufacturing a capacitor of a semiconductor device. In order to reduce a vertical etching profile at a lower portion of a hole where a charge storage electrode, an impurity is doped into the interlayer insulating film wherein the difference in concentration of the impurity at a lower portion and at an upper portion of the interlayer insulating film is controlled to make the etching rate at the lower portion of the interlayer insulating film faster than that at the upper portion of the interlayer insulating film using a wet etching process. Therefore, the region where a lower electrode will be formed has a maximum width to prevent a decrease in the capacitance of the capacitor.

9. 发明授权

US06924229B2 Method for forming a semiconductor device with a hard mask layer formed over a bit line to protect the bit line during subsequent etching steps 失效
标题翻译：用于形成具有形成在位线上的硬掩模层的半导体器件以在随后的蚀刻步骤期间保护位线的方法
公开(公告)号：US06924229B2
公开(公告)日：2005-08-02
申请号：US10608426
申请日：2003-06-30
申请人： Jung Taik Cheong , Sang Do Lee , Bong Ho Choi
发明人： Jung Taik Cheong , Sang Do Lee , Bong Ho Choi
IPC分类号： H01L21/3205 , H01L21/60 , H01L21/8242 , H01L27/108 , H01L21/4757
CPC分类号： H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： A method for forming a semiconductor device having improved characteristics and reliability by forming a hard mask layer on a bit line to prevent degradation of characteristics of the device in a self-alignment contact process of a storage electrode is disclosed. The hard mask layer utilizes over-hang formed at the upper portion of the bit line so as to provide sufficient protection for the bit line in the subsequent etching processes.
摘要翻译：公开了一种通过在位线上形成硬掩模层来形成具有改进的特性和可靠性的半导体器件的方法，以防止存储电极的自对准接触过程中器件的特性劣化。硬掩模层利用在位线的上部形成的过悬垂，以便在随后的蚀刻工艺中为位线提供足够的保护。

10. 发明申请

US20050153535A1 Method for forming contact in semiconductor device 失效
标题翻译：在半导体器件中形成接触的方法
公开(公告)号：US20050153535A1
公开(公告)日：2005-07-14
申请号：US10882698
申请日：2004-06-29
申请人： Chang-Youn Hwang , Bong-Ho Choi , Jung-Geun Kim
发明人： Chang-Youn Hwang , Bong-Ho Choi , Jung-Geun Kim
IPC分类号： H01L21/28 , H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/44 , H01L21/4763 , H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/02052 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L21/76801 , H01L21/76802 , H01L21/76831
摘要： Disclosed is a method for forming a contact in a semiconductor device. The method includes the steps of: forming a bit line on a substrate; forming an oxide layer made of high density plasma (HDP) oxide on a substrate structure including the bit line and the substrate; forming a hard mask on the oxide layer; and performing an etching process for forming a storage node contact, wherein the etching process is performed after the bit line, the oxide layer and the hard mask are formed with a predetermined thickness and a predetermined tensile stress such that a total compressive stress value of the bit line, the oxide layer and the hard mask layer is less than a critical value of a lifting phenomenon.
摘要翻译：公开了一种在半导体器件中形成接触的方法。该方法包括以下步骤：在衬底上形成位线; 在包括所述位线和所述衬底的衬底结构上形成由高密度等离子体（HDP）氧化物制成的氧化物层; 在氧化物层上形成硬掩模; 以及进行用于形成存储节点接触的蚀刻工艺，其中在所述位线，所述氧化物层和所述硬掩模形成预定厚度和预定拉伸应力之后执行所述蚀刻工艺，使得所述蚀刻工艺的总压缩应力值位线，氧化物层和硬掩模层小于提升现象的临界值。

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