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1. 发明授权

US5235216A Bipolar transistor using emitter-base reverse bias carrier generation 失效
标题翻译：双极晶体管采用发射极 - 反向偏置载波生成
公开(公告)号：US5235216A
公开(公告)日：1993-08-10
申请号：US729969
申请日：1991-07-15
申请人： Robert K. Cook , Bob H. Yun
发明人： Robert K. Cook , Bob H. Yun
IPC分类号： H01L29/10 , H01L29/732
CPC分类号： H01L29/1004 , H01L29/7322
摘要： A circuit for generating a negative voltage includes: a bipolar transistor including, a) an N type collector region, b) a P type base region, and c) an N type emitter region, the base region width between the emitter region and the collector region being less than about 5,000 angstroms and the dopant concentration of the base region being in the range of about 1-10.times.10.sup.18 atoms/cm.sup.3 ; means for applying a reference potential to the base region; and means for applying a bias potential to the emitter region so as to generate a negative output potential at the collector region. The circuit can likewise comprise a PNP bipolar transistor biased to generate a negative voltage. The circuit can be used on integrated circuit chips to provide a complementary voltage, thereby obviating the requirement for separate, complementary power supplies.
摘要翻译：用于产生负电压的电路包括：双极晶体管，包括：a）N型集电极区域，b）P型基极区域，以及c）N型发射极区域，发射极区域与集电极之间的基极区域宽度区域小于约5,000埃，碱性区域的掺杂剂浓度在约1-10×10 18原子/ cm 3的范围内; 用于向基区施加参考电位的装置; 以及用于向发射极区域施加偏置电位以在集电极区域产生负输出电位的装置。该电路同样可以包括偏置以产生负电压的PNP双极晶体管。该电路可用于集成电路芯片以提供互补电压，从而避免了单独的互补电源的需求。

2. 发明授权

US4274909A Method for forming ultra fine deep dielectric isolation 失效
标题翻译：形成超细深电介质隔离的方法
公开(公告)号：US4274909A
公开(公告)日：1981-06-23
申请号：US130882
申请日：1980-03-17
申请人： Krishnamur Venkataraman , Bob H. Yun
发明人： Krishnamur Venkataraman , Bob H. Yun
IPC分类号： H01L21/76 , H01L21/033 , H01L21/308 , H01L21/331 , H01L21/762 , H01L29/73 , H01L21/20 , H01L21/22
CPC分类号： H01L21/76205 , H01L21/0337 , H01L21/0338 , H01L21/308 , H01L21/3088 , Y10S148/051 , Y10S148/085 , Y10S148/117 , Y10S148/131 , Y10S438/947
摘要： A method is shown for forming ultra fine, deep dielectric isolation in a silicon body. The method involves forming a first layer of material on the silicon body over a first set of alternately designated device regions. A conformal coating is deposited over the first layer and on the silicon body included in a second set of alternately designated device regions and the designated isolation regions. The thickness of the conformal coating is chosen to be substantially the width of the planned isolation between device regions. A second layer is then deposited over the conformal coating. The first layer and conformal coating are composed of different materials. The topmost surface comprising of the second layer and the conformal coating is planarized by removing partially the second layer and conformal coating from the first layer wherein the second set of alternately designated device regions in the silicon body are covered by the conformal coating and the second layer with portions of the conformal coating separating the covers for the first and second set of device regions. The portions of the conformal coating separating the covers are removed down to the silicon body over the designated isolation regions. A groove is then etched in the silicon body using the covers as the etch mask. The groove is etched to the desired depth of the dielectric isolation in the designated isolation regions and then is filled typically by thermal oxidation.
摘要翻译：示出了在硅体中形成超细，深电介质隔离的方法。该方法包括在第一组交替指定的器件区上在硅体上形成第一层材料。在第一层和第二组交替指定的器件区域和指定的隔离区域中的硅体上沉积保形涂层。保形涂层的厚度被选择为基本上设备区域之间的计划隔离的宽度。然后将第二层沉积在保形涂层上。第一层和保形涂层由不同的材料组成。包括第二层和保形涂层的最上表面通过从第一层部分地去除第二层和保形涂层来平坦化，其中硅体中的第二组交替指定的器件区域被保形涂层覆盖，第二层其中保形涂层的部分分离用于第一和第二组装置区域的盖。将覆盖物的共形涂层的部分在指定的隔离区域下移到硅体上。然后使用覆盖物作为蚀刻掩模在硅体中蚀刻凹槽。将凹槽蚀刻到指定隔离区域中的介电隔离的期望深度，然后通常通过热氧化填充。

3. 发明授权

US4325025A Automated channel doping measuring circuit 失效
标题翻译：自动通道掺杂测量电路
公开(公告)号：US4325025A
公开(公告)日：1982-04-13
申请号：US152226
申请日：1980-05-22
申请人： Richard A. Corcoran , William A. Keenan , Demetrios Michaelides , Bob H. Yun
发明人： Richard A. Corcoran , William A. Keenan , Demetrios Michaelides , Bob H. Yun
IPC分类号： G01N27/00 , G01N27/04 , G01R31/26 , H01L21/66 , G01R27/26
CPC分类号： G01R31/2639
摘要： An apparatus for measuring the surface potential and impurity concentration in a semi-conductor body by monitoring the current flowing in a semiconductor body when the body is biased with a ramp voltage above its flat band voltage and summing the monitored current with the ramp voltage biasing the body. The apparatus provides direct measurement of surface potential and impurity concentration in a semiconductor structure and is especially useful in metal insulator semiconductor (MIS) structures.
摘要翻译：一种用于通过监测半导体本体中流动的电流来测量半导体体中的表面电位和杂质浓度的装置，当体被斜坡电压高于其平带电压并且将所监视的电流与斜坡电压相加时身体。该装置提供对半导体结构中的表面电位和杂质浓度的直接测量，并且在金属绝缘体半导体（MIS）结构中特别有用。

4. 发明授权

US5194397A Method for controlling interfacial oxide at a polycrystalline/monocrystalline silicon interface 失效
标题翻译：在多晶/单晶硅界面处理界面氧化物的方法
公开(公告)号：US5194397A
公开(公告)日：1993-03-16
申请号：US710498
申请日：1991-06-05
申请人： Robert K. Cook , Ronald W. Knepper , Subodh K. Kulkarni , Russell C. Lange , Paul A. Ronsheim , Seshadri Subbanna , Manu J. Tejwani , Bob H. Yun
发明人： Robert K. Cook , Ronald W. Knepper , Subodh K. Kulkarni , Russell C. Lange , Paul A. Ronsheim , Seshadri Subbanna , Manu J. Tejwani , Bob H. Yun
IPC分类号： H01L21/205 , H01L21/225 , H01L21/285 , H01L21/316 , H01L21/331 , H01L29/73 , H01L29/732
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02307 , H01L21/2256 , H01L21/28525 , H01L21/31662 , Y10S148/017 , Y10S148/124 , Y10S438/974
摘要： A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.

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