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1. 发明授权

US08768270B2 High linearity TX/RX switch 有权
标题翻译：高线性TX / RX开关
公开(公告)号：US08768270B2
公开(公告)日：2014-07-01
申请号：US13494175
申请日：2012-06-12
申请人： Bevin George Perumana , Saikat Sarkar , Michael Boers
发明人： Bevin George Perumana , Saikat Sarkar , Michael Boers
IPC分类号： H04B1/44
CPC分类号： H04B1/525
摘要： A TX/RX switch includes a first switching device connectable with a power amplifier and a second switching device connectable with a low noise amplifier. Both the first switching device and the second switching device are operating in an ON state in transmit mode to provide substantial linearity including no significant alternating current signal swing across any two nodes of the first switching device and the second switching device in the ON state.
摘要翻译： TX / RX开关包括可与功率放大器连接的第一开关装置和可与低噪声放大器连接的第二开关装置。第一开关器件和第二开关器件都在发送模式下工作在接通状态，以提供基本上的线性，包括在处于导通状态的第一开关器件和第二开关器件的任何两个节点上没有显着的交流信号摆幅。

2. 发明申请

US20100093299A1 ANALOG SIGNAL PROCESSOR IN A MULTI-GIGABIT RECEIVER SYSTEM 有权
标题翻译：多功能接收机系统中的模拟信号处理器
公开(公告)号：US20100093299A1
公开(公告)日：2010-04-15
申请号：US12447163
申请日：2007-10-25
申请人： Stephane Pinel , Joy Laskar , David Yeh , Bevin George Perumana , Saikat Sarkar
发明人： Stephane Pinel , Joy Laskar , David Yeh , Bevin George Perumana , Saikat Sarkar
IPC分类号： H04B17/00 , H04B1/16
CPC分类号： G06G7/12
摘要： An analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits quadrature phase shift keying (QPSK) modulated using a CMOS (complementary metal-oxide semiconductor) process. Further, an analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits binary phase shift keying (BPSK), minimum shift keying (MSK), and/or amplitude shift keying (ASK) signal modulated in CMOS processes.
摘要翻译：可以实现模拟多吉比特接收机和/或收发机用于使用CMOS（互补金属氧化物半导体）工艺调制的多吉比特正交相移键控（QPSK）的接收和解调。此外，可以实现模拟多吉比特接收机和/或收发器用于接收和解调多吉比特二进制相移键控（BPSK），最小移位键控（MSK）和/或幅度键控（ASK）信号调制在CMOS工艺中。

3. 发明申请

US20130331043A1 HIGH LINEARITY TX/RX SWITCH 有权
标题翻译：高线性TX / RX开关
公开(公告)号：US20130331043A1
公开(公告)日：2013-12-12
申请号：US13494175
申请日：2012-06-12
申请人： Bevin George Perumana , Saikat Sarkar , Michael Boers
发明人： Bevin George Perumana , Saikat Sarkar , Michael Boers
IPC分类号： H04B1/44
CPC分类号： H04B1/525
摘要： A TX/RX switch includes a first switching device connectable with a power amplifier and a second switching device connectable with a low noise amplifier. Both the first switching device and the second switching device are operating in an ON state in transmit mode to provide substantial linearity including no significant alternating current signal swing across any two nodes of the first switching device and the second switching device in the ON state.
摘要翻译： TX / RX开关包括可与功率放大器连接的第一开关装置和可与低噪声放大器连接的第二开关装置。第一开关器件和第二开关器件都在发送模式下工作在接通状态，以提供基本上的线性，包括在处于导通状态的第一开关器件和第二开关器件的任何两个节点上没有显着的交流信号摆幅。

4. 发明申请

US20090140784A1 HIGH-SPEED PULSE SHAPING FILTER SYSTEMS AND METHODS 有权
标题翻译：高速脉冲形状滤波器系统和方法
公开(公告)号：US20090140784A1
公开(公告)日：2009-06-04
申请号：US12327279
申请日：2008-12-03
申请人： Bevin George PERUMANA , Arun Rachamadugu , Stephane Pinel , Joy Laskar
发明人： Bevin George PERUMANA , Arun Rachamadugu , Stephane Pinel , Joy Laskar
IPC分类号： H03L7/00 , H03K5/01
CPC分类号： H03H15/00 , H03H2015/002
摘要： A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.
摘要翻译：第一系统和方法涉及使用分支系统的模拟电流模式方法。在模拟电流模式实现中，可以根据滤波器系数对多个分支系统进行缩放，并使用已知的数据点进行切换。正系数可以向求和节点添加电流，而负系数可以从求和节点去除电流。开关可以通过快速充电/放电路径实现，以便以非常高的数据速率运行。第二系统和方法涉及基于数字查找表的高速实现。在数字实现中，可以将输出预先计算为驱动n位DAC的n位输出字。 n位字的每个位可以被描述为已知数据点的独立函数。每个这样的功能可以被实现为高速组合逻辑块。这两种系统和方法使得能够实现用于千兆位/秒数据传输的脉冲整形滤波器。

5. 发明授权

US08473535B2 High-speed pulse shaping filter systems and methods 有权
标题翻译：高速脉冲整形滤波系统及方法
公开(公告)号：US08473535B2
公开(公告)日：2013-06-25
申请号：US12327279
申请日：2008-12-03
申请人： Bevin George Perumana , Arun Rachamadugu , Stephane Pinel , Joy Laskar
发明人： Bevin George Perumana , Arun Rachamadugu , Stephane Pinel , Joy Laskar
IPC分类号： G06F17/10
CPC分类号： H03H15/00 , H03H2015/002
摘要： A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.
摘要翻译：第一系统和方法涉及使用分支系统的模拟电流模式方法。在模拟电流模式实现中，可以根据滤波器系数对多个分支系统进行缩放，并使用已知的数据点进行切换。正系数可以向求和节点添加电流，而负系数可以去除求和节点的电流。开关可以通过快速充电/放电路径实现，以便以非常高的数据速率运行。第二系统和方法涉及基于数字查找表的高速实现。在数字实现中，可以将输出预先计算为驱动n位DAC的n位输出字。 n位字的每个位可以被描述为已知数据点的独立函数。每个这样的功能可以被实现为高速组合逻辑块。这两种系统和方法使得能够实现用于千兆位/秒数据传输的脉冲整形滤波器。

6. 发明授权

US08081948B2 Analog signal processor in a multi-gigabit receiver system 有权
标题翻译：模拟信号处理器在一个多吉比特接收机系统中
公开(公告)号：US08081948B2
公开(公告)日：2011-12-20
申请号：US12447163
申请日：2007-10-25
申请人： Stephane Pinel , Joy Laskar , David Yeh , Bevin George Perumana , Saikat Sarkar
发明人： Stephane Pinel , Joy Laskar , David Yeh , Bevin George Perumana , Saikat Sarkar
IPC分类号： H04B1/16
CPC分类号： G06G7/12
摘要： An analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits quadrature phase shift keying (QPSK) modulated using a CMOS (complementary metal-oxide semiconductor) process. Further, an analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits binary phase shift keying (BPSK), minimum shift keying (MSK), and/or amplitude shift keying (ASK) signal modulated in CMOS processes.
摘要翻译：可以实现模拟多吉比特接收机和/或收发机用于使用CMOS（互补金属氧化物半导体）工艺调制的多吉比特正交相移键控（QPSK）的接收和解调。此外，可以实现模拟多吉比特接收机和/或收发器用于接收和解调多吉比特二进制相移键控（BPSK），最小移位键控（MSK）和/或幅度键控（ASK）信号调制在CMOS工艺中。

7. 发明授权

US07113008B2 Frequency mixing apparatus 有权
标题翻译：混频装置
公开(公告)号：US07113008B2
公开(公告)日：2006-09-26
申请号：US11222011
申请日：2005-09-08
申请人： Bevin George Perumana , Sudipto Chakraborty , Chang-Ho Lee , Joy Laskar , Sang-Hyun Woo
发明人： Bevin George Perumana , Sudipto Chakraborty , Chang-Ho Lee , Joy Laskar , Sang-Hyun Woo
IPC分类号： H03B19/00
CPC分类号： H03D7/125
摘要： A frequency mixing apparatus is provided. In the frequency mixing apparatus, a PMOS transistor is coupled to an NMOS transistor in a cascode configuration and an LO signal is applied to the bulks of the PMOS and NMOS transistors so that an input signal applied to their gates is mixed with the LO signal. High isolation between the bulks and gates of the transistors resulting from application of the LO signal to the bulks prevents leakage of the LO signal, thereby decreasing a DC offset voltage. This renders the frequency mixing applicable to a DCR. Also, due to the cascade configuration similar to an inverter configuration, the frequency mixing apparatus can be incorporated in an FPGA of a MODEM in SDR applications. Frequency mixing based on switching of a threshold voltage decreases a noise factor and enables frequency mixing in a low supply voltage range, thereby decreasing power consumption.
摘要翻译：提供了一种混频装置。在频率混合装置中，PMOS晶体管以共源共栅配置耦合到NMOS晶体管，并且LO信号施加到PMOS和NMOS晶体管的体积，使得施加到其栅极的输入信号与LO信号混合。通过将LO信号施加到体积而产生的晶体管的大块和栅极之间的高隔离防止了LO信号的泄漏，从而减小了DC偏移电压。这使得频率混合适用于DCR。另外，由于与逆变器配置相似的级联配置，所以可将混频装置并入SDR应用中的MODEM的FPGA中。基于阈值电压的切换的频率混合降低了噪声因子，并且能够在低电源电压范围内进行频率混合，从而降低功耗。

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