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1. 发明申请

US20140246701A1 Flexible, space-efficient I/O circuitry for integrated circuits 有权
公开(公告)号：US20140246701A1
公开(公告)日：2014-09-04
申请号：US13627506
申请日：2012-09-26
申请人： Baysand Inc.
发明人： Jonathan C. Parks , Yin Hao Liew , Kok Seong Lee , Salah M. Werfelli
IPC分类号： H01L27/118 , G06F17/50
CPC分类号： H03K19/1732 , H01L24/06 , H01L2224/05553 , H01L2225/06513 , H01L2225/06541 , H01L2924/00 , H01L2924/0002 , H03K19/1736
摘要： Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.

2. 发明授权

US09590634B1 Metal configurable hybrid memory 有权
标题翻译：金属可配置混合存储器
公开(公告)号：US09590634B1
公开(公告)日：2017-03-07
申请号：US15181007
申请日：2016-06-13
申请人： BaySand Inc.
发明人： Jonathan C. Park , Yau Kok Lai , Teck Siong Ong , Yin Hao Liew
IPC分类号： H03K19/177 , H01L27/118 , H03K19/00 , H03K19/173 , G11C7/10
CPC分类号： H03K19/17724 , G11C5/025 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/222 , G11C2207/104 , G11C2207/108 , H01L27/11582 , H01L27/11807 , H01L28/00 , H01L2027/11812 , H01L2027/11838 , H01L2027/11881 , H03K19/0008 , H03K19/1731 , H03K19/1776
摘要： Embodiments of the invention relate to a metal configurable hybrid memory for use in integrated circuit designs for implementation in structured ASIC or similar platforms utilizing a base cell or standard cell. In accordance with certain aspects, a hybrid memory according to embodiments of the invention utilizes a fixed custom memory core and a customizable peripheral set of base cells. In accordance with these and further aspects, the hybrid memory can be specified using a macro, in which certain memory features (e.g. ECC, etc.) are implemented using the customizable peripheral set of base cells, and which may be selected or omitted from the design by the user. This enables the overall logic use for the memory to be optimized for a user's particular design. Unused logic in the customizable peripheral set of base cells can thus be freed for top-level logic use, thereby optimizing the design according to a user's functional and dimensional requirements and minimizing unnecessary waste of silicon area and power.
摘要翻译：本发明的实施例涉及用于集成电路设计中的金属可配置混合存储器，用于在使用基本单元或标准单元的结构化ASIC或类似平台中实现。根据某些方面，根据本发明的实施例的混合存储器利用固定的定制存储器核心和可定制的基站单元集合。根据这些和另外的方面，可以使用宏来指定混合存储器，其中使用可定制的基本单元的集合来实现某些存储器特征（例如ECC等），并且可以从由用户设计。这使得为用户的特定设计优化了存储器的整体逻辑使用。因此，可定制的基本单元集合中的未使用的逻辑可以被释放以用于顶级逻辑使用，从而根据用户的功能和尺寸要求优化设计，并且最小化不必要的硅面积和功率浪费。

3. 发明申请

US20150048425A1 Gate array architecture with multiple programmable regions 审中-公开
标题翻译：具有多个可编程区域的门阵列架构
公开(公告)号：US20150048425A1
公开(公告)日：2015-02-19
申请号：US14336996
申请日：2014-07-21
申请人： Baysand Inc.
发明人： Jonathan C. Park , Salah M. Werfelli , WeiZhi Kang , Wan Tat Hooi , Kok Siong Tee , Jeremy Jia Jian Lee
IPC分类号： H01L27/118 , H01L27/02
CPC分类号： H01L27/11807 , G06F17/5054 , H01L27/0207 , H01L2027/11888
摘要： An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.
摘要翻译：集成电路包括具有二维逻辑门阵列的门阵列层，每个逻辑门包括多个晶体管。至少一个上部基于模板的金属层耦合到栅极阵列层并且被配置为限定配电网络，时钟网络和全局信号网络中的至少一个。在设计集成电路之前，上部基于模板的金属层的迹线的构造至少主要是预定的。

4. 发明授权

US09577640B1 Flexible, space-efficient I/O circuitry for integrated circuits 有权
标题翻译：灵活，节省空间的集成电路I / O电路
公开(公告)号：US09577640B1
公开(公告)日：2017-02-21
申请号：US14293401
申请日：2014-06-02
申请人： Baysand Inc.
发明人： Jonathan C Park , Yin Hao Liew , Kok Seong Lee , Salah M Werfelli
IPC分类号： H03K19/173 , H01L25/00 , H01L23/50 , H01L23/522 , H01L27/02 , H01L23/00
CPC分类号： H03K19/1736 , H01L23/50 , H01L23/5226 , H01L24/06 , H01L27/0296 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2924/14 , H01L2924/1431 , H03K19/1732
摘要： Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. In other aspects, ESD circuitry is provided at corners of the IC layout and optionally within selected I/O slots. Decap circuitry is provided at an outer edge of the IC layout and is scalable in order to meet different requirements.
摘要翻译：灵活，节省空间的集成电路I / O架构简化了电路设计并缩短了设计时间。在一个方面，消除用于电源焊盘的电池，部分地通过将这些焊盘的ESD电路定位在焊盘本身下方，仅留下信号I / O缓冲器。耦合到信号I / O缓冲器的焊盘可以根据定制电路被定义为信号I / O焊盘或电源焊盘。定制电路还提供灵活的银行架构，其中银行内的信号I / O缓冲区共享电源要求可能与另一个银行不同。灵活地定义了存储体的数量和属于每个存储体的信号I / O缓冲器的数量。在其他方面，ESD电路被提供在IC布局的角落处，并且可选地在选定的I / O槽内。解码电路在IC布局的外边缘提供，并且是可扩展的，以满足不同的要求。

5. 发明授权

US08773163B1 Flexible, space-efficient I/O circuitry for integrated circuits 有权
标题翻译：灵活，节省空间的集成电路I / O电路
公开(公告)号：US08773163B1
公开(公告)日：2014-07-08
申请号：US13627591
申请日：2012-09-26
申请人： Baysand Inc.
发明人： Jonathan C Park , Yin Hao Liew , Kok Seong Lee , Salah M Werfelli
IPC分类号： H03K19/173
CPC分类号： H03K19/1732 , H01L24/06 , H01L2224/05553 , H01L2225/06513 , H01L2225/06541 , H01L2924/00 , H01L2924/0002 , H03K19/1736
摘要： Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.
摘要翻译：灵活，节省空间的集成电路I / O架构简化了电路设计并缩短了设计时间。在一个方面，消除用于电源焊盘的电池，部分地通过将这些焊盘的ESD保护电路定位在焊盘本身下方，仅留下信号I / O缓冲器。耦合到信号I / O缓冲器的焊盘可以根据定制电路被定义为信号I / O焊盘或电源焊盘。定制电路还提供灵活的银行架构，其中银行内的信号I / O缓冲区共享电源要求，可能与另一银行的信号I / O缓冲区的电源要求不同。灵活地定义了存储体的数量和属于每个存储体的信号I / O缓冲器的数量。定制电路还提供柔性焊盘选项，由此IC焊盘可被配置用于不同的封装技术，例如用于倒装芯片焊接的引线接合或用于其它类型的接合。

6. 发明申请

US20130334576A1 Gate array architecture with multiple programmable regions 有权
标题翻译：具有多个可编程区域的门阵列架构
公开(公告)号：US20130334576A1
公开(公告)日：2013-12-19
申请号：US13970873
申请日：2013-08-20
申请人： Baysand Inc.
发明人： Jonathan C Park , Salah M Werfelli , WeiZhi Kang , Wan Tat Hooi , Kok Siong Tee , Jeremy Jia Jian Lee
IPC分类号： H01L27/088 , G06F17/50
CPC分类号： H01L27/088 , G06F17/5054 , G06F17/5077 , H01L27/0207 , H01L27/11807 , H01L2027/11888
摘要： An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces attic upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.
摘要翻译：集成电路包括具有二维逻辑门阵列的门阵列层，每个逻辑门包括多个晶体管。至少一个上部基于模板的金属层耦合到栅极阵列层并且被配置为限定配电网络，时钟网络和全局信号网络中的至少一个。在集成电路的设计之前，至少主要是预先确定了上层基于模板的金属层的构造。

7. 发明授权

US08875080B1 Programmable macros for metal/via programmable gate array integrated circuits 有权
标题翻译：用于金属/可编程门阵列集成电路的可编程宏
公开(公告)号：US08875080B1
公开(公告)日：2014-10-28
申请号：US14096292
申请日：2013-12-04
申请人： Baysand Inc.
发明人： Jonathan C Parks , Yin Hao Liew , Jeremy Lee Jia Jian
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A design methodology is provided to fully automate the creation of multiple-personality programmable macros for use in metal/via programmable ICs. Programmability is achieved using programmable switches, each of which may include one or more metal traces and/or vias on one or more layers configured in series, in parallel, or in combination. Multiple overlapping switches may exist in the same location. That is, switches may be defined that use some of the same resources. Any one of the switches may be “turned on,” while the remaining switches remain turned off. As part of the design methodology, different nets or parts of an electrical circuit design are programmed by replacing the switches with hard connections that close the circuit, or with no connections so as to open the circuit, or cause the circuit to remain open. The methodology allows for sharing routing or programming resources to achieve optimize layout area usage.
摘要翻译：提供了一种设计方法，以完全自动化创建用于金属/通过可编程IC的多个性可编程宏。使用可编程开关实现可编程性，每个开关可以包括串联，并联或组合配置的一个或多个层上的一个或多个金属迹线和/或通孔。多个重叠开关可能存在于同一位置。也就是说，可以定义使用一些相同资源的交换机。任何一个开关都可以“打开”，而剩余的开关保持关闭。作为设计方法的一部分，通过用闭合电路的硬连接替换开关或者没有连接以打开电路或使电路保持开路来编程不同的网络或电路设计的部分。该方法允许共享路由或编程资源以实现优化布局区域的使用。

8. 发明申请

US20140247525A1 Flexible, space-efficient I/O circuitry for integrated circuits 审中-公开
公开(公告)号：US20140247525A1
公开(公告)日：2014-09-04
申请号：US13627270
申请日：2012-09-26
申请人： BAYSAND INC.
发明人： Jonathan C. Parks , Yin Hao Liew , Kok Seong Lee , Salah M. Werfelli
IPC分类号： H01L25/00 , H02H9/04 , G06F17/50
CPC分类号： H03K19/1732 , H01L24/06 , H01L2224/05553 , H01L2225/06513 , H01L2225/06541 , H01L2924/00 , H01L2924/0002 , H03K19/1736
摘要： Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.

9. 发明申请

US20140246702A1 Flexible, space-efficient I/O circuitry for integrated circuits 有权
公开(公告)号：US20140246702A1
公开(公告)日：2014-09-04
申请号：US13627624
申请日：2012-09-26
申请人： Baysand Inc.
发明人： Jonathan C Parks , Yin Hao Liew , Kok Seong Lee , Salah M Werfelli
IPC分类号： H01L27/118 , G06F17/50
CPC分类号： H03K19/1732 , H01L24/06 , H01L2224/05553 , H01L2225/06513 , H01L2225/06541 , H01L2924/00 , H01L2924/0002 , H03K19/1736
摘要： Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.

10. 发明授权

US08788984B2 Gate array architecture with multiple programmable regions 有权
标题翻译：具有多个可编程区域的门阵列架构
公开(公告)号：US08788984B2
公开(公告)日：2014-07-22
申请号：US13970873
申请日：2013-08-20
申请人： Baysand Inc.
发明人： Jonathan C Park , Salah M Werfelli , WeiZhi Kang , Wan Tat Hooi , Kok Siong Tee , Jeremy Jia Jian Lee
IPC分类号： G06F17/50
CPC分类号： H01L27/088 , G06F17/5054 , G06F17/5077 , H01L27/0207 , H01L27/11807 , H01L2027/11888
摘要： An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.
摘要翻译：集成电路包括具有二维逻辑门阵列的门阵列层，每个逻辑门包括多个晶体管。至少一个上部基于模板的金属层耦合到栅极阵列层并且被配置为限定配电网络，时钟网络和全局信号网络中的至少一个。在设计集成电路之前，上部基于模板的金属层的迹线的构造至少主要是预定的。

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