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1. 发明授权

US5763316A Substrate isolation process to minimize junction leakage 失效
标题翻译：衬底隔离工艺，以减少结漏电
公开(公告)号：US5763316A
公开(公告)日：1998-06-09
申请号：US800977
申请日：1997-02-19
申请人： Sen-Fu Chen , Bao-Ru Yang , Wen-Cheng Chang
发明人： Sen-Fu Chen , Bao-Ru Yang , Wen-Cheng Chang
IPC分类号： H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76216 , H01L21/32
摘要： A process for creating field oxide isolation for the micron and sub-micron devices in the high density integrated circuits has been developed. The junction leakage problem resulted from the trenches in the substrate formed after the removal of the silicon nitride mask, is avoided. The encroachment of the "bird's beak" into the small active device region is also minimized by this invention. These goals are accomplished by the addition of a polysilicon or amorphous silicon refill layer in the trenches after the removal of the silicon nitride oxidation mask in the isolation region, prior to field oxide oxidation process.
摘要翻译：已经开发了用于在高密度集成电路中为微米和亚微米器件创建场氧化物隔离的工艺。避免了在去除氮化硅掩模之后形成的衬底中的沟槽产生的结漏电问题。本发明也将“鸟嘴”侵入小活动装置区域也被最小化。这些目标通过在场氧化物氧化过程之前在隔离区域中去除氮化硅氧化掩模之后，在沟槽中添加多晶硅或非晶硅填充层来实现。

2. 发明授权

US5639342A Method of monitoring and controlling a silicon nitride etch step 失效
标题翻译：监测和控制氮化硅蚀刻步骤的方法
公开(公告)号：US5639342A
公开(公告)日：1997-06-17
申请号：US616416
申请日：1996-03-15
申请人： Sen Fu Chen , Wen Cheng Chang , Heng Hsin Liu , Bao Ru Yang
发明人： Sen Fu Chen , Wen Cheng Chang , Heng Hsin Liu , Bao Ru Yang
IPC分类号： H01L21/311 , H01L21/66 , H01L21/00
CPC分类号： H01L22/24 , H01L21/31105 , H01L22/20
摘要： A patterned silicon nitride layer formed over a semiconductor integrated circuit wafer having a layer of pad oxide is often used as a mask for subsequent processing steps. Etching of the silicon nitride layer is difficult to control and can create defects in the pad oxide layer which are difficult to detect before the manufacture of the semiconductor integrated circuit wafer is completed. A method is described using potassium hydroxide treatment and scanning electron microscope evaluation of a test wafer for detection of defects at the silicon nitride etching step. Continued processing of defective wafers can be terminated and the silicon nitride etching step can be controlled using this method.
摘要翻译：在具有垫氧化物层的半导体集成电路晶片上形成的图案化氮化硅层经常用作后续处理步骤的掩模。氮化硅层的蚀刻难以控制，并且可能在半导体集成电路晶片的制造完成之前在衬垫氧化物层中产生难以检测的缺陷。使用氢氧化钾处理和扫描电子显微镜评价在氮化硅蚀刻步骤中检测缺陷的测试晶片的方法。可以终止对缺陷晶片的继续处理，并且可以使用该方法来控制氮化硅蚀刻步骤。

3. 发明授权

US5904570A Method for polymer removal after etching 失效
标题翻译：蚀刻后聚合物去除的方法
公开(公告)号：US5904570A
公开(公告)日：1999-05-18
申请号：US650357
申请日：1996-05-20
申请人： Sen-Fu Chen , Bao-Ru Yang , Wen-Cheng Chang , Heng-Hsin Liu
发明人： Sen-Fu Chen , Bao-Ru Yang , Wen-Cheng Chang , Heng-Hsin Liu
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/306
CPC分类号： H01L21/02071
摘要： The polymeric residues which remain after the plasma-enhanced subtractive etching of polycrystalline layers in reactive halogen-containing gases are removed by a combination ashing in oxygen gas and subsequent removal with an organic solvent.
摘要翻译：在反应性含卤素气体中的多晶层的等离子体增强的减去蚀刻之后残留的聚合物残余物通过氧气中的灰分组合并随后用有机溶剂去除而被除去。

4. 发明授权

US06227211B1 Uniformity improvement of high aspect ratio contact by stop layer 有权
标题翻译：通过停止层的高纵横比接触的均匀性提高
公开(公告)号：US06227211B1
公开(公告)日：2001-05-08
申请号：US09206740
申请日：1998-12-07
申请人： Bao Ru Yang , Wen-Chuan Chiang , James Jann-Ming Wu
发明人： Bao Ru Yang , Wen-Chuan Chiang , James Jann-Ming Wu
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , H01L21/76816
摘要： The poor uniformity of Interlevel Dielectric Deposition (ILD) thickness for High Aspect Ratio (HAR) contact after Chemical Mechanical Planarization (CMP) will cause serious underlayer loss due to the longer over-etching time that is required to compensate for thickness differences within the wafer. Prior Art uses 1.5K Plasma Enhanced Tetra-Ethyl-Ortho-Silicate (PETEOS) to serve as a stop layer and thus reduce underlayer loss. The present invention teaches using a non-silicon oxide containing SiN/SiON or Si3N4/SiON as a stop layer. The present invention therefore is aimed at reducing underlayer loss and thereby improving the uniformity of the underlayer thickness upon completion of the hole etching process. Concurrently, the over-etch time can be reduced to less than 10% of the time required for Prior Art contact hole etching.
摘要翻译：化学机械平面化（CMP）后高纵横比（HAR）接触的层间介电沉积（ILD）厚度差的均匀性将导致严重的底层损耗，这是由于需要更长的过蚀刻时间来补偿晶片内的厚度差异。现有技术使用1.5K等离子体增强四乙基 - 正硅酸盐（PETEOS）作为停止层，从而减少底层损失。本发明教导了使用含有SiN / SiON或Si3N4 / SiON的非氧化硅作为停止层。因此，本发明旨在减少底层损失，从而在孔蚀刻工艺完成时提高底层厚度的均匀性。同时，过蚀刻时间可以减少到现有技术接触孔蚀刻所需时间的10％以下。

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