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1. 发明申请

US20160182015A1 FRACTIONAL AND INTEGER RATIO POLYPHASE INTERPOLATION FILTER 审中-公开
标题翻译：分数和整数比多相插值滤波器
公开(公告)号：US20160182015A1
公开(公告)日：2016-06-23
申请号：US14576149
申请日：2014-12-18
申请人： Vinay Gupta , Arvind Kaushik , Akshat Mittal , Amrit P. Singh
发明人： Vinay Gupta , Arvind Kaushik , Akshat Mittal , Amrit P. Singh
IPC分类号： H03H17/02
CPC分类号： H03H17/0685 , H03H17/0275
摘要： A fractional and integer ratio polyphase interpolation filter changes the sample rate of an input digital signal by a ratio defined by an interpolation rate, M, and a decimation rate, N. The clock rate required to evaluate the output signal is M/N.
摘要翻译：分数和整数比多相插值滤波器通过由内插速率M和抽取率N定义的比例来改变输入数字信号的采样率。评估输出信号所需的时钟速率为M / N。

2. 发明申请

US20150016444A1 WIRELESS COMMUNICATION APPARATUS AND METHOD 有权
标题翻译：无线通信装置和方法
公开(公告)号：US20150016444A1
公开(公告)日：2015-01-15
申请号：US13938239
申请日：2013-07-10
申请人： Sachin Jain , Somvir Dahiya , Arvind Garg , Arvind Kaushik , Arindam Sinha
发明人： Sachin Jain , Somvir Dahiya , Arvind Garg , Arvind Kaushik , Arindam Sinha
IPC分类号： H04W56/00
CPC分类号： H04W56/001
摘要： A transmission node for use in a wireless communication network includes a first register for storing a set of first mask bits, a second register for storing a set of second mask bits, and a mask switching block for multiplexing the set of first mask bits and the set of second mask bits and outputting the set of third mask bits. The transmission node further includes a CPRI unit with an auxiliary interface for receiving the set of third mask bits. An activation block is connected between the CPRI unit and the mask switching block for causing the mask switching block to output the set of second mask bits based on data in a current frame in the CPRI unit.
摘要翻译：用于无线通信网络的传输节点包括用于存储一组第一掩码位的第一寄存器，用于存储一组第二掩码位的第二寄存器和用于复用该组第一掩码位的掩码切换块一组第二掩码位并输出该组第三掩码位。传输节点还包括具有用于接收该组第三掩码位的辅助接口的CPRI单元。激活块连接在CPRI单元和掩码切换块之间，用于使得掩码切换块基于CPRI单元中的当前帧中的数据输出第二掩码位集合。

3. 发明授权

US09665510B2 Synchronous bus architecture for digital pre-distortion system 有权
公开(公告)号：US09665510B2
公开(公告)日：2017-05-30
申请号：US14580158
申请日：2014-12-22
申请人： Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
发明人： Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
IPC分类号： G06F13/24 , G06F13/28 , H03F1/32 , H04B1/04
CPC分类号： G06F13/24 , G06F13/28 , H03F1/3247 , Y02D10/14
摘要： A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.

4. 发明申请

US20150146626A1 METHOD FOR ADDING LEAF NODE TO MULTI-NODE BASE STATION 有权
标题翻译：将叶节点添加到多节点基站的方法
公开(公告)号：US20150146626A1
公开(公告)日：2015-05-28
申请号：US14092881
申请日：2013-11-27
申请人： Arindam Sinha , Somvir Dahiya , Arvind Garg , Sachin Jain , Arvind Kaushik
发明人： Arindam Sinha , Somvir Dahiya , Arvind Garg , Sachin Jain , Arvind Kaushik
IPC分类号： H04L5/00 , H04W16/18 , H04W56/00
CPC分类号： H04W16/18 , H04L5/008 , H04W56/001
摘要： Adding a new subsystem node to a multi-node base station topology (e.g., a chain or tree topology) in a telecommunications network can disrupt the effective operation of the existing multi-node base station. By accurately measuring the timing difference between uplink and downlink signaling across a current terminating node during the configuration of the new terminating node, the new node can be added with reduced impact upon the operation of the existing base station nodes.
摘要翻译：将新的子系统节点添加到电信网络中的多节点基站拓扑（例如，链或树拓扑）可能会破坏现有多节点基站的有效操作。通过在新的终止节点的配置期间准确地测量跨当前终止节点的上行链路和下行链路信令之间的定时差异，可以增加新节点对现有基站节点的操作的影响。

5. 发明申请

US20160179715A1 SYNCHRONOUS BUS ARCHITECTURE FOR DIGITAL PRE-DISTORTION SYSTEM 有权
标题翻译：数字预失真系统同步总线架构
公开(公告)号：US20160179715A1
公开(公告)日：2016-06-23
申请号：US14580158
申请日：2014-12-22
申请人： Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
发明人： Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
IPC分类号： G06F13/24 , G06F13/28
CPC分类号： G06F13/24 , G06F13/28 , H03F1/3247 , Y02D10/14
摘要： A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.
摘要翻译：用于将预失真输出样本存储在存储器中的系统包括采样计数器，编程接口模块和比较器。样本计数器对预失真的输出样本进行计数，生成动态计数值，接收捕获计数器状态信号，并生成第一个计数值。编程接口模块接收并输出第一计数值，偏移值和捕获控制信号，并产生第一中断信号。比较器接收第一计数值，偏移值，动态计数值和捕获控制信号，生成最终值，将最终值与动态计数值进行比较，并在最终值等于动态计数值时产生触发信号基于捕获控制信号的计数值。触发信号启动将预失真输出样本存储在存储器中。

6. 发明授权

US09231530B1 System for calibrating power amplifier 有权
标题翻译：功率放大器校准系统
公开(公告)号：US09231530B1
公开(公告)日：2016-01-05
申请号：US14591928
申请日：2015-01-08
申请人： Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
发明人： Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
IPC分类号： H04K1/02 , H04L25/03 , H04L25/49 , H03F1/32 , H04B1/04
CPC分类号： H04B1/0475 , H03F1/3241 , H03F1/3247 , H03F3/24 , H03F2200/321 , H04B17/13 , H04B2001/0425 , H04W52/362
摘要： A system for calibrating a power amplifier (PA) includes a memory, a processor, a digital pre-distorter (DPD), and a data converter. The DPD includes a programming interface module, a pattern generator, a multiplier, and a pre-distorter module. The multiplier multiplies reference baseband stream data from the memory with pattern coefficient data generated by the pattern generator to generate shaped reference baseband stream data. The pre-distorter module generates pre-distorted shaped reference baseband stream data. The PA receives a low-power reference radio frequency (RF) signal corresponding to the pre-distorted shaped reference baseband stream data and generates a high-power reference RF signal. The processor receives and compares the pre-distorted shaped reference baseband stream data with amplified shaped reference baseband stream data corresponding to the high-power reference RF signal, and adjusts pre-distortion parameters in the pre-distorter module based on the comparison such that the PA generates a linear high-power RF signal.
摘要翻译：用于校准功率放大器（PA）的系统包括存储器，处理器，数字预失真器（DPD）和数据转换器。 DPD包括编程接口模块，模式发生器，乘法器和预失真器模块。乘法器将来自存储器的参考基带流数据与由模式发生器产生的模式系数数据相乘以产生形状参考基带流数据。预失真器模块生成预失真的参考基带流数据。 PA接收与预失真的参考基带流数据相对应的低功率参考射频（RF）信号，并产生高功率参考RF信号。处理器接收并比较预失真的参考基带流数据与对应于大功率参考RF信号的放大的成形参考基带流数据，并且基于比较调整预失真器模块中的预失真参数，使得 PA产生线性高功率RF信号。

7. 发明授权

US09088941B2 Wireless communication apparatus and method 有权
标题翻译：无线通信装置及方法
公开(公告)号：US09088941B2
公开(公告)日：2015-07-21
申请号：US13938248
申请日：2013-07-10
申请人： Arvind Garg , Somvir Dahiya , Sachin Jain , Arvind Kaushik , Arindam Sinha
发明人： Arvind Garg , Somvir Dahiya , Sachin Jain , Arvind Kaushik , Arindam Sinha
IPC分类号： H04W56/00 , H04L12/863
CPC分类号： H04W56/001 , H04L47/622
摘要： A transmission node for use in a wireless communication network includes a first CPRI unit for transmitting auxiliary data to a second CPRI unit in the transmission node. A memory unit stores control word data of the auxiliary data. A memory write block is connected between the first CPRI unit and the memory unit for writing the control word data to the memory unit based on a first set of frame timing signals received from the first CPRI unit. A memory read and merge block is connected to the memory unit for reading the control word data stored in the memory unit based on a second set of frame timing signals, merging the control word data with IQ data, and transmitting the merged auxiliary data to the second CPRI unit.
摘要翻译：用于无线通信网络的传输节点包括用于将辅助数据发送到传输节点中的第二CPRI单元的第一CPRI单元。存储单元存储辅助数据的控制字数据。存储器写入块连接在第一CPRI单元和存储器单元之间，用于基于从第一CPRI单元接收的第一组帧定时信号将控制字数据写入存储器单元。存储器读和合并块连接到存储器单元，用于基于第二组帧定时信号读取存储在存储器单元中的控制字数据，将控制字数据与IQ数据合并，并将合并的辅助数据发送到第二个CPRI单位。

8. 发明授权

US09661521B2 Interrupt handling system for cellular communication network 有权
公开(公告)号：US09661521B2
公开(公告)日：2017-05-23
申请号：US14591926
申请日：2015-01-08
申请人： Somvir Dahiya , Rajan Kapoor , Arvind Kaushik
发明人： Somvir Dahiya , Rajan Kapoor , Arvind Kaushik
IPC分类号： H04B1/16 , H04W28/02 , G06F13/24 , H04J3/06
CPC分类号： H04W28/0205 , G06F13/24 , H04B1/16 , H04J3/0685 , H04L25/03 , H04L49/90 , H04L49/9084 , H04W28/0278 , H04W88/085
摘要： A system for merging first and second interrupts includes first and second queue modules, first and second status modules, and first and second merger modules. The first and second queue modules receive first and second en-queue signals corresponding to the first and second interrupts, first and second de-queue signals, and generate first and second status signals. The first and second status modules receive first and second status signals, and first and second output signals, and generate first and second merge signals. The first and second merger modules receive the first and second merge signals, and generate the first and second output signals. One of the first and second output signals is indicative of the first and second en-queue signals, thereby merging the first and second interrupts into at least one of the first and second output signals.

9. 发明申请

US20160041579A1 TIMING SYNCHRONIZATION CIRCUIT FOR WIRELESS COMMUNICATION APPARATUS 有权
标题翻译：用于无线通信设备的同步同步电路
公开(公告)号：US20160041579A1
公开(公告)日：2016-02-11
申请号：US14452535
申请日：2014-08-06
申请人： Inayat Ali , Arvind Kaushik , Sachin Prakash , Arindam Sinha
发明人： Inayat Ali , Arvind Kaushik , Sachin Prakash , Arindam Sinha
IPC分类号： G06F1/12 , G06F1/08
CPC分类号： G06F1/08 , G06F1/10 , H03J7/00 , H03L7/00 , H04B15/00
摘要： A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock.
摘要翻译：传输节点包括提供用于基于JESD204B的数据传输的功能时钟的数字前端设备。前端装置包括用于基于前端装置的装置时钟产生锁相时钟的PLL，用于通过分相锁相时钟产生功能时钟的时钟分割部，连接在PLL之间的时钟门控装置和时钟分割单元，以及用于定时无线帧边界的系统参考信号采样单元。时钟门控单元门锁相锁定时钟，以便在锁定PLL或接收系统重新同步请求时，将功能时钟与相位锁定时钟的预定数量周期内的器件时钟对准。系统参考信号采样单元在设备时钟和锁相时钟之间以零周期等待时间采样系统参考信号。

10. 发明授权

US09204312B2 Method for adding leaf node to multi-node base station 有权
标题翻译：叶节点添加到多节点基站的方法
公开(公告)号：US09204312B2
公开(公告)日：2015-12-01
申请号：US14092881
申请日：2013-11-27
申请人： Arindam Sinha , Somvir Dahiya , Arvind Garg , Sachin Jain , Arvind Kaushik
发明人： Arindam Sinha , Somvir Dahiya , Arvind Garg , Sachin Jain , Arvind Kaushik
IPC分类号： H04L5/00 , H04W16/18 , H04W56/00
CPC分类号： H04W16/18 , H04L5/008 , H04W56/001
摘要： Adding a new subsystem node to a multi-node base station topology (e.g., a chain or tree topology) in a telecommunications network can disrupt the effective operation of the existing multi-node base station. By accurately measuring the timing difference between uplink and downlink signaling across a current terminating node during the configuration of the new terminating node, the new node can be added with reduced impact upon the operation of the existing base station nodes.
摘要翻译：将新的子系统节点添加到电信网络中的多节点基站拓扑（例如，链或树拓扑）可能会破坏现有多节点基站的有效操作。通过在新的终止节点的配置期间准确地测量跨当前终止节点的上行链路和下行链路信令之间的定时差异，可以增加新节点对现有基站节点的操作的影响。

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