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1. 发明申请

US20120125666A1 MULTI-LAYERED PRINTED CIRCUIT BOARD WITH CONDUCTIVE TEST AREAS AS WELL AS METHOD FOR DETERMINING A MISALIGNMENT OF AN INNER LAYER 审中-公开
标题翻译：具有导电测试领域的多层印刷电路板作为确定内层缺陷的方法
公开(公告)号：US20120125666A1
公开(公告)日：2012-05-24
申请号：US13291674
申请日：2011-11-08
申请人： Arno KLAMMINGER , Heinz Habenbacher , Wilhelm Lobner
发明人： Arno KLAMMINGER , Heinz Habenbacher , Wilhelm Lobner
IPC分类号： H05K1/00
CPC分类号： H05K1/0268 , H05K3/429 , H05K3/4638 , H05K2201/09781 , H05K2203/166
摘要： A multi-layered printed circuit board (1) including conductive test areas (7) on at least one inner layer (2) for determining a possible misalignment of an inner layer, or a misalignment of an inner layer structuring, respectively, wherein the conductive test areas include ring structures (7.i) arranged in rows and defining inner, non-conductive areas (8.i) of various sizes, and having through-contacting bore holes (5) in the region of the rest areas (7).
摘要翻译：一种多层印刷电路板（1），包括在至少一个内层（2）上的导电测试区域（7），用于确定内层的可能的未对准或分别构成的内层的不对准，其中导电测试区域包括排列成行并限定各种尺寸的内部不导电区域（8.i）的环形结构（7.i），并且在其余区域（7）的区域中具有通孔接触孔（5）。

2. 发明申请

US20080044127A1 Printed Circuit Board Element Comprising at Least One Optical Waveguide, and Method for the Production of Such a Printed Circuit Board Element 审中-公开
标题翻译：包括最少一个光波导的印刷电路板元件和用于制造这种印刷电路板元件的方法
公开(公告)号：US20080044127A1
公开(公告)日：2008-02-21
申请号：US10581849
申请日：2004-12-28
申请人： Gunther Leising , Arno Klamminger , Gregor Langer , Volker Schmidt , Riikka Reitzer
发明人： Gunther Leising , Arno Klamminger , Gregor Langer , Volker Schmidt , Riikka Reitzer
IPC分类号： G02B6/43 , G02B6/12
CPC分类号： G02B6/43 , G02B6/12004 , G02B6/42 , G02B6/4201 , G02B2006/1213 , G02B2006/1219 , G02B2006/12195 , H01L2224/16225 , H05K1/0274
摘要： Disclosed is a printed circuit board element comprising an optical waveguide and an embedded optoelectronic element.
摘要翻译：公开了一种包括光波导和嵌入式光电子元件的印刷电路板元件。

3. 发明申请

US20080190651A1 Multi-Layered Printed Circuit Board Comprising Conductive Test Surfaces, and Method for Determining a Misalignment of an Inner Layer 审中-公开
标题翻译：包含导电测试表面的多层印刷电路板和确定内层的不对准的方法
公开(公告)号：US20080190651A1
公开(公告)日：2008-08-14
申请号：US11883949
申请日：2006-02-23
申请人： Arno Klamminger , Heinz Habenbacher , Wilhelm Lobner
发明人： Arno Klamminger , Heinz Habenbacher , Wilhelm Lobner
IPC分类号： H05K1/00
CPC分类号： H05K1/0268 , H05K3/429 , H05K3/4638 , H05K2201/09781 , H05K2203/166
摘要： The invention relates to a multi-layered printed circuit board (1) comprising conductive test surfaces (7) on at least one inner layer (2) for determining a possible misalignment of an inner layer or an inner layer structuring, the conductive test surfaces consisting of ring structures (7.i) which are arranged in a row and define inner non-conductive different-sized surfaces (8.i). The inventive printed circuit board also comprises metallised boreholes (5) in the region of the test surfaces. If there is no misalignment or only negligible misalignment, said boreholes (5) are located in the region of the inner, non-conductive surfaces (8.i). However, in the event of non-negligible misalignment, at least one borehole (5) is located in the region of one of the conductive ring structures (7.i) and thus comprises a conductive connection to the ring structure (7.i). The test surface ring structures (7.i) are divided into segments (a, b, c, d) in the peripheral direction, said segments (a, b, c, d) being separated from each other in the peripheral direction by non-conductive separating regions (9).
摘要翻译：本发明涉及一种多层印刷电路板（1），其包括在至少一个内层（2）上的导电测试表面（7），用于确定内层或内层结构的可能的未对准，导电测试表面环形结构（7.i），其布置成一排并限定内部不导电的不同尺寸的表面（8.i）。本发明的印刷电路板还包括在测试表面的区域中的金属化的钻孔（5）。如果没有未对准或仅可忽略的未对准，则所述钻孔（5）位于内部非导电表面（8.i）的区域中。然而，在不可忽视的未对准的情况下，至少一个钻孔（5）位于导电环结构（7.i）之一的区域中，并且因此包括与环结构（7a）的导电连接，。测试表面环结构（7.i）在圆周方向上分成段（a，b，c，d），所述段（a，b，c，d）在周向方向上彼此分离，导电分离区域（9）。

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