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1. 发明授权

US08789043B2 Optimized placement planning for virtual machines in a network by breaking relocation graph into one or more cores to apply different solutions 失效
标题翻译：通过将重定位图拆分成一个或多个内核来应用不同的解决方案，优化了网络中虚拟机的布局规划
公开(公告)号：US08789043B2
公开(公告)日：2014-07-22
申请号：US12912805
申请日：2010-10-27
申请人： Ofer Biran , Ari Freund , Erez Hadad , Evgeny Hazanovich , Yosef Moatti
发明人： Ofer Biran , Ari Freund , Erez Hadad , Evgeny Hazanovich , Yosef Moatti
IPC分类号： G06F9/455 , G06F9/46
CPC分类号： G06F9/45558 , G06F9/5066 , G06F9/5077 , G06F2009/4557
摘要： Methods and systems for generating a placement plan for one or more virtual machines (VMs) in a computing environment are provided. The method comprises providing, to a computing system, input parameters comprising a current placement for the one or more VMs on one or more hosts in a computing network; a target placement that assigns at least one of the one or more VMs to at least another host in said one or more hosts; and a set of constraints with which both the current placement and the target placement comply.
摘要翻译：提供了用于在计算环境中为一个或多个虚拟机（VM）生成放置计划的方法和系统。该方法包括向计算系统提供包括计算网络中的一个或多个主机上的一个或多个VM的当前位置的输入参数; 将所述一个或多个VM中的至少一个VM分配给所述一个或多个主机中的至少另一个主机的目标布局; 以及当前展示位置和目标展示位置都符合的一组约束条件。

2. 发明申请

US20070011631A1 Harnessing machine learning to improve the success rate of stimuli generation 有权
标题翻译：利用机器学习提高刺激生成的成功率
公开(公告)号：US20070011631A1
公开(公告)日：2007-01-11
申请号：US11177127
申请日：2005-07-07
申请人： Shai Fine , Ari Freund , Itai Jaeger , Yehuda Naveh , Avi Ziv
发明人： Shai Fine , Ari Freund , Itai Jaeger , Yehuda Naveh , Avi Ziv
IPC分类号： G06F17/50
CPC分类号： G01R31/318357
摘要： Test generation is improved by learning the relationship between an initial state vector for a stimuli generator and generation success. A stimuli generator for a design-under-verification is provided with information about the success probabilities of potential assignments to an initial state bit vector. Selection of initial states according to the success probabilities ensures a higher success rate than would be achieved without this knowledge. The approach for obtaining an initial state bit vector employs a CSP solver. A learning system is directed to model the behavior of possible initial state assignments. The learning system develops the structure and parameters of a Bayesian network that describes the relation between the initial state and generation success.
摘要翻译：通过学习刺激发生器的初始状态向量与生成成功之间的关系来提高测试生成。提供了一种用于未验证设计的刺激发生器，其中提供了关于初始状态位向量的潜在分配的成功概率的信息。根据成功概率选择初始状态确保比没有这种知识将获得的成功率更高的成功率。用于获得初始状态位向量的方法采用CSP求解器。学习系统旨在模拟可能的初始状态分配的行为。学习系统开发了贝叶斯网络的结构和参数，描述了初始状态与发电成功之间的关系。

3. 发明授权

US07331007B2 Harnessing machine learning to improve the success rate of stimuli generation 有权
标题翻译：利用机器学习提高刺激生成的成功率
公开(公告)号：US07331007B2
公开(公告)日：2008-02-12
申请号：US11177127
申请日：2005-07-07
申请人： Shai Fine , Ari Freund , Itai Jaeger , Yehuda Naveh , Avi Ziv
发明人： Shai Fine , Ari Freund , Itai Jaeger , Yehuda Naveh , Avi Ziv
IPC分类号： G06F11/00 , G06F17/50
CPC分类号： G01R31/318357
摘要： Test generation is improved by learning the relationship between an initial state vector for a stimuli generator and generation success. A stimuli generator for a design-under-verification is provided with information about the success probabilities of potential assignments to an initial state bit vector. Selection of initial states according to the success probabilities ensures a higher success rate than would be achieved without this knowledge. The approach for obtaining an initial state bit vector employs a CSP solver. A learning system is directed to model the behavior of possible initial state assignments. The learning system develops the structure and parameters of a Bayesian network that describes the relation between the initial state and generation success.
摘要翻译：通过学习刺激发生器的初始状态向量与生成成功之间的关系来提高测试生成。提供了一种用于未验证设计的刺激发生器，其中提供了关于初始状态位向量的潜在分配的成功概率的信息。根据成功概率选择初始状态确保比没有这种知识将获得的成功率更高的成功率。用于获得初始状态位向量的方法采用CSP求解器。学习系统旨在模拟可能的初始状态分配的行为。学习系统开发了贝叶斯网络的结构和参数，描述了初始状态与发电成功之间的关系。

4. 发明申请

US20120042311A1 OPTIMIZED PLACEMENT PLANNING FOR VIRTUAL MACHINES IN A NETWORK 失效
标题翻译：网络虚拟机优化布局规划
公开(公告)号：US20120042311A1
公开(公告)日：2012-02-16
申请号：US12912805
申请日：2010-10-27
申请人： Ofer Biran , Ari Freund , Erez Hadad , Evgeny Hazanovich , Yosef Moatti
发明人： Ofer Biran , Ari Freund , Erez Hadad , Evgeny Hazanovich , Yosef Moatti
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F9/5066 , G06F9/5077 , G06F2009/4557
摘要： Methods and systems for generating a placement plan for one or more virtual machines (VMs) in a computing environment are provided. The method comprises providing, to a computing system, input parameters comprising a current placement for the one or more VMs on one or more hosts in a computing network; a target placement that assigns at least one of the one or more VMs to at least another host in said one or more hosts; and a set of constraints with which both the current placement and the target placement comply.
摘要翻译：提供了用于在计算环境中为一个或多个虚拟机（VM）生成放置计划的方法和系统。该方法包括向计算系统提供包括计算网络中的一个或多个主机上的一个或多个VM的当前位置的输入参数; 将所述一个或多个VM中的至少一个VM分配给所述一个或多个主机中的至少另一个主机的目标布局; 以及当前展示位置和目标展示位置都符合的一组约束条件。

5. 发明授权

US08234615B2 Constraint programming based method for bus-aware macro-block pin placement in a hierarchical integrated circuit layout 有权
标题翻译：总线感知宏块引脚放置在分层集成电路布局中的基于约束编程的方法
公开(公告)号：US08234615B2
公开(公告)日：2012-07-31
申请号：US12849973
申请日：2010-08-04
申请人： Shyam Ramji , Bella Dubrov , Haggai Eran , Ari Freund , Edward F. Mark , Timothy A. Schell
发明人： Shyam Ramji , Bella Dubrov , Haggai Eran , Ari Freund , Edward F. Mark , Timothy A. Schell
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/06
摘要： Assigning pins to macro-blocks of an Integrated Circuit (IC) chip is described. The macro-block pin assignments are automatically placed using Constraint Programming (CP) techniques to position the pins on the periphery of a macro-block. Bus-ordering and pin-spacing constraints are performed considering all the nets forming the IC design simultaneously. The CP formulation includes modeling detailed and discrete constraints required to achieve an optimal pin-assignment. A stochastic CSP solver is used to define the cost function on search points giving full assignments to all the variables. The macro-block pins are ultimately moved to computed locations.
摘要翻译：描述了将引脚分配给集成电路（IC）芯片的宏块。使用约束编程（CP）技术自动放置宏块引脚分配，以将引脚定位在宏块的外围。考虑到同时形成IC设计的所有网络，执行总线排序和引脚间距约束。 CP公式包括建立实现最佳引脚分配所需的详细和离散约束。随机CSP求解器用于定义搜索点上的成本函数，给出所有变量的完整分配。宏块引脚最终移动到计算位置。

6. 发明申请

US20120036491A1 Constraint Programming Based Method for Bus-Aware Macro-Block Pin Placement in a Hierarchical Integrated Circuit Layout 有权
标题翻译：在基于分层集成电路布局的总线感知宏块引脚放置的基于约束编程的方法
公开(公告)号：US20120036491A1
公开(公告)日：2012-02-09
申请号：US12849973
申请日：2010-08-04
申请人： Shyam Ramji , Bella Dubrov , Eran Haggai , Ari Freund , Edward F. Mark , Timothy A. Schell
发明人： Shyam Ramji , Bella Dubrov , Eran Haggai , Ari Freund , Edward F. Mark , Timothy A. Schell
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/06
摘要： Assigning pins to macro-blocks of an Integrated Circuit (IC) chip is described. The macro-block pin assignments are automatically placed using Constraint Programming (CP) techniques to position the pins on the periphery of a macro-block. Bus-ordering and pin-spacing constraints are performed considering all the nets forming the IC design simultaneously. The CP formulation includes modeling detailed and discrete constraints required to achieve an optimal pin-assignment. A stochastic CSP solver is used to define the cost function on search points giving full assignments to all the variables. The macro-block pins are ultimately moved to computed locations.
摘要翻译：描述了将引脚分配给集成电路（IC）芯片的宏块。使用约束编程（CP）技术自动放置宏块引脚分配，以将引脚定位在宏块的外围。考虑到同时形成IC设计的所有网络，执行总线排序和引脚间距约束。 CP公式包括建立实现最佳引脚分配所需的详细和离散约束。随机CSP求解器用于定义搜索点上的成本函数，给出所有变量的完整分配。宏块引脚最终移动到计算位置。

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