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1. 发明申请

US20120319747A1 PHASE-LOCKED LOOP LOCK DETECT 有权
标题翻译：相位锁定锁定检测
公开(公告)号：US20120319747A1
公开(公告)日：2012-12-20
申请号：US13164098
申请日：2011-06-20
申请人： Ardeshir Namdar-Mehdiabadi , Yong Hee Lee , Thomas Obkircher
发明人： Ardeshir Namdar-Mehdiabadi , Yong Hee Lee , Thomas Obkircher
IPC分类号： H03L7/095
CPC分类号： H03L7/095 , H03L7/18
摘要： Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time.
摘要翻译：公开了一种用于检测锁相环（PLL）锁定的装置和方法。一方面，锁定检测部件包括参考乘法器和锁定检测。参考乘法器可以接收由PLL产生的VCO产生的分频器信号，分频器信号和由VCO产生的压控振荡器（VCO）输出。参考乘法器还可以使用参考信号和VCO输出产生相乘的参考信号。倍增的参考信号可以具有作为参考信号的频率的整数倍的频率。锁定检测可以至少部分地基于将从延迟的参考信号产生的信号与从延迟的分频器信号产生的信号相比较预定的时间段来检测参考信号和分频器信号的锁相。

2. 发明授权

US08456206B2 Phase-locked loop lock detect 有权
标题翻译：锁相环锁定检测
公开(公告)号：US08456206B2
公开(公告)日：2013-06-04
申请号：US13164098
申请日：2011-06-20
申请人： Ardeshir Namdar-Mehdiabadi , Yong Hee Lee , Thomas Obkircher
发明人： Ardeshir Namdar-Mehdiabadi , Yong Hee Lee , Thomas Obkircher
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/18
摘要： Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time.
摘要翻译：公开了一种用于检测锁相环（PLL）锁定的装置和方法。一方面，锁定检测部件包括参考乘法器和锁定检测。参考乘法器可以接收由PLL产生的VCO产生的分频器信号，分频器信号和由VCO产生的压控振荡器（VCO）输出。参考乘法器还可以使用参考信号和VCO输出产生相乘的参考信号。倍增的参考信号可以具有作为参考信号的频率的整数倍的频率。锁定检测可以至少部分地基于将从延迟的参考信号产生的信号与从延迟的分频器信号产生的信号相比较预定的时间段来检测参考信号和分频器信号的锁相。

3. 发明授权

US07215211B2 Prescaler for a fractional-N synthesizer 有权
$Prescaler for a fractional-N synthesizer$
标题翻译：分数N合成器的预分频器
公开(公告)号：US07215211B2
公开(公告)日：2007-05-08
申请号：US11150668
申请日：2005-06-10
申请人： Tudor Lipan , Ardeshir Namdar-Mehdiabadi
发明人： Tudor Lipan , Ardeshir Namdar-Mehdiabadi
IPC分类号： H03L7/00
CPC分类号： H03L7/193 , H03K23/667 , H03K23/68 , H03L7/197
摘要： An (N−1)/N prescaler is provided, where N is an S power of 2. The prescaler uses only S flip-flops. The (N−1)/N prescaler receives a clock input from a high frequency oscillator, and provides an output line to a counter. The (N−1)/N prescaler receives a divide-by-(N−1) signal from the counter, and responsive to the divide signal, causes the prescaler to divide by a factor of (N−1); otherwise, the prescaler divides by a factor of N.
摘要翻译：提供一个（N-1）/ N预分频器，其中N是S的2倍。预分频器仅使用S个触发器。（N-1）/ N预分频器从高频振荡器接收时钟输入，并向计数器提供输出线。（N-1）/ N预分频器从计数器接收分频（N-1）信号，并响应分频信号使预分频器除以（N-1）因子; 否则，预分频器除以N的因子。

4. 发明申请

US20060280280A1 Prescaler for a fractional-N synthesizer 有权
$Prescaler for a fractional-N synthesizer$
标题翻译：分数N合成器的预分频器
公开(公告)号：US20060280280A1
公开(公告)日：2006-12-14
申请号：US11150668
申请日：2005-06-10
申请人： Tudor Lipan , Ardeshir Namdar-Mehdiabadi
发明人： Tudor Lipan , Ardeshir Namdar-Mehdiabadi
IPC分类号： H03K23/00
CPC分类号： H03L7/193 , H03K23/667 , H03K23/68 , H03L7/197
摘要： An (N−1)/N prescaler is provided, where N is an S power of 2. The prescaler uses only S flip-flops. The (N−1)/N prescaler receives a clock input from a high frequency oscillator, and provides an output line to a counter. The (N−1)/N prescaler receives a divide-by-(N−1) signal from the counter, and responsive to the divide signal, causes the prescaler to divide by a factor of (N−1); otherwise, the prescaler divides by a factor of N.
摘要翻译：提供一个（N-1）/ N预分频器，其中N是S的2倍。预分频器仅使用S个触发器。（N-1）/ N预分频器从高频振荡器接收时钟输入，并向计数器提供输出线。（N-1）/ N预分频器从计数器接收分频（N-1）信号，并响应分频信号使预分频器除以（N-1）因子; 否则，预分频器除以N的因子。

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