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1. 发明授权

US06850123B1 Circuits and methods for characterizing the speed performance of multi-input combinatorial logic 有权
标题翻译：用于表征多输入组合逻辑的速度性能的电路和方法
公开(公告)号：US06850123B1
公开(公告)日：2005-02-01
申请号：US10447132
申请日：2003-05-27
申请人： Himanshu J. Verma , Anthony P. Calderone , Richard D. Duce
发明人： Himanshu J. Verma , Anthony P. Calderone , Richard D. Duce
IPC分类号： G01R31/30 , G01R31/3183 , H03B27/00
CPC分类号： G01R31/318321 , G01R31/3016 , Y10S331/03
摘要： A test oscillator circuit separately measures the signal propagation delay for both rising and falling edges through one or more multi-input combinatorial logic circuits. A number of components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component passes signal edges to a subsequent component in the ring, so the oscillator produces an oscillating test signal in which the period relates to the delays through the components. In some embodiments, the multi-input combinatorial logic circuits emulate tri-state buffers. These embodiments characterize the speed at which these logic circuits enable and disable signal paths.
摘要翻译：测试振荡器电路通过一个或多个多输入组合逻辑电路分别测量上升沿和下降沿的信号传播延迟。多个组件配置在一个环路中，使它们一起形成一个自由运行的环形振荡器。每个同步分量将信号边沿传递到环中的后续分量，因此振荡器产生振荡测试信号，其中该周期与通过分量的延迟有关。在一些实施例中，多输入组合逻辑电路模拟三态缓冲器。这些实施例表征了这些逻辑电路启用和禁用信号路径的速度。

2. 发明授权

US06507942B1 Methods and circuits for testing a circuit fabrication process for device uniformity 有权
标题翻译：用于测试器件均匀性的电路制造工艺的方法和电路
公开(公告)号：US06507942B1
公开(公告)日：2003-01-14
申请号：US09613494
申请日：2000-07-11
申请人： Anthony P. Calderone , Feng Wang , Tho Le La
发明人： Anthony P. Calderone , Feng Wang , Tho Le La
IPC分类号： G06F1750
CPC分类号： H01L22/34
摘要： Described are systems and methods for measuring the size uniformity of circuit features defined by the critical dimension of an integrated-circuit fabrication process. An integrated circuit is configured to include a number of oscillators, each occupying a region of the integrated circuit. Each oscillator oscillates at a frequency that depends on the critical dimension of features in the region in which it is formed. Consequently, the critical dimensions of regions across the surface of the integrated circuit can be mapped and compared by comparing the oscillation frequencies of identical oscillators formed in various regions of the integrated circuit. In programmable logic devices, oscillators can be implemented using programmable logic resources. In other embodiments, small, simple oscillators can be placed at various locations on the integrated circuit.
摘要翻译：描述了用于测量由集成电路制造工艺的关键尺寸限定的电路特征的尺寸均匀性的系统和方法。集成电路被配置为包括多个振荡器，每个振荡器占据集成电路的一个区域。每个振荡器以取决于其形成区域中的特征的临界尺寸的频率振荡。因此，可以通过比较在集成电路的各个区域中形成的相同振荡器的振荡频率来映射和比较集成电路表面上的区域的临界尺寸。在可编程逻辑器件中，可以使用可编程逻辑资源实现振荡器。在其他实施例中，小的简单振荡器可以放置在集成电路上的各个位置。

3. 发明授权

US06594610B1 Fault emulation testing of programmable logic devices 失效
标题翻译：可编程逻辑器件的故障仿真测试
公开(公告)号：US06594610B1
公开(公告)日：2003-07-15
申请号：US09853351
申请日：2001-05-11
申请人： Shahin Toutounchi , Anthony P. Calderone , Zhi-Min Ling , Robert D. Patrie , Eric J. Thorne , Robert W. Wells
发明人： Shahin Toutounchi , Anthony P. Calderone , Zhi-Min Ling , Robert D. Patrie , Eric J. Thorne , Robert W. Wells
IPC分类号： G06F1900
CPC分类号： G01R31/318519 , G01R31/318342
摘要： A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.
摘要翻译：新的测试方法使用现场可编程门阵列来模拟故障，而不是使用单独的计算机来模拟故障。在一个实施例中，选择几个（例如，两个或三个）已知的良好FPGA。在FPGA配置的设计中引入了一个故障。将配置加载到FPGA中。应用测试向量并评估结果。如果结果与无故障配置的结果不同，则会发现故障。这种方法的一个应用是评估故障覆盖。公开了可用于本发明的故障模型。

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