专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4439737A Phase locked loop, as for MPSK signal detector 失效
标题翻译：锁相环，如MPSK信号检测器
公开(公告)号：US4439737A
公开(公告)日：1984-03-27
申请号：US370580
申请日：1982-04-21
申请人： Anthony Mattei
发明人： Anthony Mattei
IPC分类号： H04L27/00 , H04L27/227 , H03D3/18 , H03D3/24
CPC分类号： H04L27/2273 , H04L2027/0067
摘要： Oscillators phase locked to transitions in the envelope of a bandwidth-limited complex waveform are used, for example, in detecting MPSK signals. The magnitude of the envelope is approximated by linearly combining the real and imaginary components of the complex waveform, or by selecting the larger of the two components, or by using both these techniques in combination.
摘要翻译：例如在检测MPSK信号中使用锁相到带宽限制复波形的包络中的转换的振荡器。通过线性组合复波形的实分量和虚分量，或通过选择两个分量中的较大者，或通过组合使用这两种技术来近似包络的大小。

2. 发明授权

US4438521A Automatically adaptive transversal filter 失效
标题翻译：自适应横向滤波器
公开(公告)号：US4438521A
公开(公告)日：1984-03-20
申请号：US385920
申请日：1982-06-07
申请人： Anthony Mattei
发明人： Anthony Mattei
IPC分类号： H04L25/03 , H04B3/18
CPC分类号： H04L25/03038
摘要： A method and apparatus for the adaptive equalizing of phase and amplitude distortion in a received signal by an N-stage digital delay line system and comprising the steps of digitally sampling the received signal and advancing each digital sample through successive stages of the N-stage digital delay line, producing a continuously up-dated scaled error signal after each advance of the digital samples in the delay line, multiplying the digital sample in each delay line stage by the scaled error signal after each sampling advance to produce a first scaled signal in each stage, separately accumulating the first scaled signals of each stage after each sampling advance, scaling and accumulating the accumulations of the first scaled signals of each stage after each M accumulations thereof to produce a weighting tap signal for each stage of the delay line, multiplying the received samples by the weighting tap signal of each stage to produce a weighted sampling for each stage, summing the weighted samplings to produce a summed signal, quantizing the summed signal to a selected quantum value which is selected in accordance with the relative value of the summed signal to the ideal quantum value, and determining and scaling the difference between the summed signal and the quantum value to produce the scaled error signal.
摘要翻译：一种用于通过N级数字延迟线系统对接收信号中的相位和幅度失真进行自适应均衡的方法和装置，包括以下步骤：对接收到的信号进行数字采样并使每个数字采样通过N级数字延迟线，在延迟线中的数字采样的每次提前之后产生连续更新的缩放误差信号，在每个采样提前之后，将每个延迟线级中的数字采样乘以缩放的误差信号，以在每个延迟线中产生第一定标信号在每次采样提前之后，分别累积各级的第一次缩放信号，在每次M次累积之后对每一级的第一次缩放信号的累积进行缩放和累加，以产生延迟线的每一级的加权抽头信号，通过每个级的加权抽头信号接收样本，以产生每个级的加权采样，将weig相加用于产生求和信号，将求和信号量化为根据求和信号与理想量子值的相对值选择的选定量子值，以及确定和缩放求和信号与量子值之间的差值以产生缩放的误差信号。

3. 发明授权

US3952187A Circuit for transforming rectangular coordinates to polar coordinates 失效
标题翻译：将直角坐标转换为极坐标的电路
公开(公告)号：US3952187A
公开(公告)日：1976-04-20
申请号：US591224
申请日：1975-06-27
申请人： John L. Robinson , Anthony Mattei
发明人： John L. Robinson , Anthony Mattei
IPC分类号： G06F1/03 , H04L27/22 , H04L27/38 , G06F7/38 , G06G7/22
CPC分类号： G06F1/03 , H04L27/38 , G06F2101/06
摘要： A circuit for transforming to polar coordinate form first and second binary number electrical signals representative of rectangular coordinates or quadrature components for a vector or phasor. The circuit utilizes a programmable memory in which values corresponding to the sine and cosine functions are stored. In the preferred form, the circuit utilizes binary number electrical signals of 10 bits. The most significant bit of the polar coordinate angle is found directly from the binary number representing one of the quadrature components, whereas the next two most significant bits of the angle are found using logic circuitry in association with the binary number signals representing the quadrature components. The remaining bits of the angle are found by use of a successive approximation technique in conjunction with the values stored in the memory. Once the angle is determined, the amplitude of the vector or phasor is determined by the use of the function P = Im(sin.theta.) + Re(cos.theta.) where Im and Re are the quadrature components. The coordinate transforming circuit is particularly useful in digital transmission and receiving systems in connection with modulation of transmitted signals and demodulation of received signals.
摘要翻译：用于转换为极坐标的电路形成代表向量或相量的直角坐标或正交分量的第一和第二二进制数电信号。该电路利用可编程存储器，其中存储对应于正弦和余弦函数的值。在优选的形式中，该电路使用10位的二进制数电信号。极坐标角的最高有效位直接从表示正交分量之一的二进制数发现，而角度的接下来的两个最高有效位是使用表示正交分量的二进制数信号的逻辑电路来找到的。通过使用逐次逼近技术结合存储在存储器中的值来找到角度的其余位。一旦确定了角度，则通过使用函数P = Im（sinθ）+ Re（cosθ）来确定矢量或相量的幅度，其中Im和Re是正交分量。坐标变换电路在与传输信号的调制和接收信号的解调有关的数字传输和接收系统中特别有用。

4. 发明授权

US3980873A Digital convolutional filter 失效
标题翻译：数字卷积滤波器
公开(公告)号：US3980873A
公开(公告)日：1976-09-14
申请号：US591229
申请日：1975-06-27
申请人： Anthony Mattei
发明人： Anthony Mattei
IPC分类号： G06F17/15 , H03H17/02 , H03H17/06 , G06F7/38 , G06F15/34
CPC分类号： H03H17/06 , H03H17/0225
摘要： A digital linear phase shift convolutional filter for filtering a series of binary number electrical signals each of which represents the magnitude of a sample of an analog electrical signal sampled at a predetermined rate. The convolutional filter utilizes a bidirectional shift register and a preferably unidirectional shift register. Each of the registers has a plurality of stages. The bidirectional shift register receives the serially presented binary number electrical signals representative of the sample magnitudes, and these samples are sequentially transferred from the output stage of the bidirectional shift register to the input stage of the unidirectional shift register. During the interval between receipt in the bidirectional shift register of binary number electrical signals representative of the sample amplitudes, the binary number electrical signals stored in the bidirectional shift register are shifted in a recirculating fashion, as are the binary number electrical signals stored in the unidirectional shift register. The binary number electrical signals appearing in particular stages of each of the registers are combined arithmetically to produce a resultant binary number electrical signal with each shift in the recirculating shift registers. These resultant signals are multiplied by constant values representing filter weights, and the products are summed to produce an output binary number electrical signal. One such output signal is produced for each new sample that enters the bidirectional shift register.
摘要翻译：一种数字线性相移卷积滤波器，用于对一系列二进制数电信号进行滤波，每个二进制数电信号表示以预定速率采样的模拟电信号的采样幅值。卷积滤波器使用双向移位寄存器和优选的单向移位寄存器。每个寄存器具有多个级。双向移位寄存器接收表示采样幅度的串行显示的二进制数电信号，并将这些采样从双向移位寄存器的输出级依次传送到单向移位寄存器的输入级。在表示采样幅度的二进制数电气信号的双向移位寄存器的接收间隔期间，存储在双向移位寄存器中的二进制数电信号以循环方式移位，存储在单向中的二进制数电信号移位寄存器出现在每个寄存器的特定级中的二进制数电信号被算术地组合以产生在循环移位寄存器中的每个移位的合成的二进制数电信号。将这些结果信号乘以表示滤波器权重的常数值，并将乘积相加以产生输出二进制数电信号。对于进入双向移位寄存器的每个新采样产生一个这样的输出信号。

5. 发明授权

US3949301A Digital click removal and squelch control circuit for an FM receiver 失效
标题翻译：用于FM接收机的数字点击移除和静噪控制电路
公开(公告)号：US3949301A
公开(公告)日：1976-04-06
申请号：US591223
申请日：1975-06-27
申请人： Anthony Mattei
发明人： Anthony Mattei
IPC分类号： H03D3/00 , H03G3/34 , H04B1/10 , H04L27/14
CPC分类号： H04B1/10 , H03D3/007 , H03G3/348 , H03D3/006
摘要： A digital click removal and squelch control circuit for a digital FM receiver. The digital receiver generates a series of binary number electrical signals each of which is representative of the instantaneous phase angle of a received frequency-modulated electrical signal or signal derived therefrom. The phase angle signals are differentiated to produce binary number electrical signals that represent the rate of change of phase angle, or, the instantaneous frequency of the received signal. During a given time interval, the phase change caused by the modulation of the received signal must be within a range determined by the bandwidth of the received frequency-modulated signal. Phase changes outside of this range represent electrical noise or clicks and are removed by the click removal circuit of the invention. If a predetermined number of clicks occur during a predetermined time interval, the squelch control circuit of the invention provides a squelch control signal which may be used to disable the output of the FM receiver. When the click rate decreases, the output of the FM receiver is restored.
摘要翻译：用于数字FM接收机的数字点击删除和静噪控制电路。数字接收机产生一系列二进制数电信号，每个二进制数电信号表示接收的调频电信号或从其得到的信号的瞬时相位角。相位角信号被微分以产生表示相位角变化率或接收信号的瞬时频率的二进制数电信号。在给定的时间间隔期间，由接收信号的调制引起的相位变化必须在由接收的调频信号的带宽确定的范围内。在该范围之外的相位变化表示电噪声或点击，并且由本发明的点击去除电路去除。如果在预定时间间隔期间发生预定次数的点击，则本发明的静噪控制电路提供静噪控制信号，其可用于禁止FM接收机的输出。当点击率降低时，FM接收机的输出被恢复。

6. 发明授权

US4475220A Symbol synchronizer for MPSK signals 失效
标题翻译：符号同步器用于MPSK信号
公开(公告)号：US4475220A
公开(公告)日：1984-10-02
申请号：US340771
申请日：1982-01-19
申请人： Anthony Mattei , William L. Hahn, Jr.
发明人： Anthony Mattei , William L. Hahn, Jr.
IPC分类号： H04L7/02 , H03D3/22 , H03L7/06
CPC分类号： H04L7/0054
摘要： A symbol synchronizer, as for use with apparatus for detecting MPSK signals to provide complex sampled data descriptive of keying signal phase, in which the timing of the resampling can be controlled with resolution that is a fraction of the time between successive complex data samples.The symbol synchronizer uses a first digital controlled oscillator to recover the MPSK baseband signal sampled at a frequency f.sub.i rate. The MPSK signal is operated on to recover a sampled data description of the envelope of the MPSK signal sampled at a frequency f.sub.s, which may equal f.sub.i or be down-sampled therefrom. This is digitally filtered to provide a sampled data locking signal to a second digital controlled oscillator, which uses modular arithmetic to generate a digital sampled data description at f.sub.s rate of a sawtooth waveform repetitive at f.sub.k keying rate. In this second digital-controlled oscillator an adder sums its output as delayed by a full f.sub.s clock cycle, the error signal, and a constant term. The output of this adder (ignoring the overflow, to implement the modular arithmetic) is the sawtooth waveform with f.sub.k fundamental frequency subsequently used in the symbol synchronizer. The sawtooth waveform in sampled data form is adapted for digital phase shifting by linearly combining it with a programmable phase correction signal in sampled data form. The shifted waveform is used as the carrier signal for resampling the MPSK signal to provide complex samples, phased locked to f.sub.k keying rate, for application to the circuitry for deciding the keying phase of the received MPSK signal.
摘要翻译：符号同步器，用于检测MPSK信号以提供描述键控信号相位的复杂采样数据的装置，其中可以用分辨率来控制重采样的定时，分辨率是连续的复数数据采样之间的时间的一部分。符号同步器使用第一数字控制振荡器来恢复以频率倍率采样的MPSK基带信号。操作MPSK信号以恢复以可以相等于或从其采样的频率fs采样的MPSK信号的包络的采样数据描述。这被数字滤波以向第二数字控制振荡器提供采样的数据锁定信号，该第二数字控制振荡器使用模数运算来以fk键控速率以锯齿波形重复的fs速率产生数字采样数据描述。在该第二数字控制振荡器中，加法器将其输出延迟了全fs时钟周期，误差信号和常数项。该加法器的输出（忽略溢出，实现模运算）是随后在符号同步器中使用fk基频的锯齿波形。采样数据形式的锯齿波形适用于通过采样采样数据形式将其与可编程相位校正信号线性组合进行数字相移。移位波形用作载波信号，用于对MPSK信号进行重新采样，以提供复杂采样，锁相到fk锁定速率，以应用于用于确定接收的MPSK信号的密钥相位的电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式