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1. 发明授权

US06134642A Direct memory access (DMA) data transfer requiring no processor DMA support 失效
标题翻译：直接存储器访问（DMA）数据传输，不需要处理器DMA支持
公开(公告)号：US06134642A
公开(公告)日：2000-10-17
申请号：US698191
申请日：1996-08-15
申请人： Anthony John Holmes , Mark Elliott , Ian Nicholas Cottam , John Harper , Martin Stratford
发明人： Anthony John Holmes , Mark Elliott , Ian Nicholas Cottam , John Harper , Martin Stratford
IPC分类号： G06F13/28 , G06F13/14
CPC分类号： G06F13/28
摘要： A digital system has a main memory 10 with a main memory access (DMA) unit 11 through which data channels 12, 13 are coupled to the memory. A processor system (processor 14, RAM data memory 15, instruction memory 16) is also coupled to the memory through a read/write buffer 20, each read stalling the processor for typically 5 cycles. For block reads, a block memory read unit 25 is connected in parallel with the path between the read/write buffer 20 and the DMA unit 11. This block read unit can be set from the processor 14 with a block start address and a block length passed as writes through the read/write buffer 20. The block is read (first phase) word by word from the main memory via the DMA unit into a memory 28 in the block read unit. The processor then sends a command to the block read unit as a read through the read/write buffer, which then writes the block word by word directly into the memory 15 (second phase), using the processor's local data and address buses 17 and 18 and disabling the processor's address buffer 32.
摘要翻译：数字系统具有主存储器10，其具有主存储器访问（DMA）单元11，数据通道12,13通过该存储器访问（DMA）单元11耦合到存储器。处理器系统（处理器14，RAM数据存储器15，指令存储器16）也通过读/写缓冲器20耦合到存储器，每个读取缓冲器读取停止处理器典型的5个周期。对于块读取，块存储器读取单元25与读/写缓冲器20和DMA单元11之间的路径并联连接。该块读取单元可以从处理器14以块起始地址和块长度通过读/写缓冲器20作为写入传递。该块从主存储器经由DMA单元逐字地读取（第一阶段）到块读取单元中的存储器28。然后处理器通过读/写缓冲器向块读单元发送命令作为读/写缓冲器，该缓冲器然后使用处理器的本地数据和地址总线17和18将块逐字写入存储器15（第二阶段）并禁用处理器的地址缓冲器32。

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