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1. 发明授权

US07724684B2 System and method for designing and implementing packet processing products 有权
标题翻译：数据包处理产品的设计与实现方法
公开(公告)号：US07724684B2
公开(公告)日：2010-05-25
申请号：US11805702
申请日：2007-05-24
申请人： Vispi Cassod , Anthony Dalleggio , Amine Kandalaft
发明人： Vispi Cassod , Anthony Dalleggio , Amine Kandalaft
IPC分类号： H04J1/16 , H04L12/56
CPC分类号： H04L41/22 , H04L41/0843 , H04L41/0879 , H04L49/10 , H04L49/30 , H04L49/3009
摘要： A system and method for allowing a user to create instructions for building a packet processing integrated circuit. The system includes a user interface for allowing a user to define a desired packet processing algorithm (4) using a plurality of discrete packet processing blocks (22, 24, 28, 30), each of the blocks corresponding to a portion of the desired packet processing algorithm (4). The system allows the user to define connections (10) between the plurality of packet processing blocks (22, 24, 28, 30). The system processes a plurality of packet processing blocks (22, 24, 28, 30) and the connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing the desired packet processing algorithm (19). The list of instructions can be delivered to a customer (12), or the customer can receive an integrated circuit constructed using the list of instructions (19), or the customer can receive a NETLIST generated using said list of instructions (16). The plurality of packet processing blocks (22, 24, 28, 30) can include a Packet Processing Unit (PPU, PPUX) 22, a Packet Modification Unit (PMU) 28, and a Decision and Forwarding Unit (DFU) 30.
摘要翻译：一种用于允许用户创建用于构建分组处理集成电路的指令的系统和方法。该系统包括用户界面，用于允许用户使用多个离散分组处理块（22,24,28,30）定义所需的分组处理算法（4），每个块对应于期望分组的一部分处理算法（4）。系统允许用户在多个分组处理块（22,24,28,30）之间定义连接（10）。系统处理多个分组处理块（22,24,28,30）和连接以提供用于产生能够执行所需分组处理算法（19）的集成电路的硬件描述语言中的指令列表。指令列表可以传递给客户（12），或者客户可以接收使用指令列表（19）构建的集成电路，或者客户可以接收使用所述指令列表（16）生成的NETLIST。多个分组处理块（22,24,28,30）可以包括分组处理单元（PPU，PPUX）22，分组修改单元（PMU）28以及决策和转发单元（DFU）30。

2. 发明授权

US06954466B1 Link-layer receiver 有权
标题翻译：链路层接收机
公开(公告)号：US06954466B1
公开(公告)日：2005-10-11
申请号：US10457175
申请日：2003-06-09
申请人： Anthony Dalleggio , Denis Rystsov
发明人： Anthony Dalleggio , Denis Rystsov
IPC分类号： H04L12/56 , H04L12/66
CPC分类号： H04L49/90
摘要： A System Packet Interface (SPI) level 4 receiver groups four consecutive 16 bit control/data words into a single 64 bit word (with a resultant rate of up to 210 MHz). The 64 bit word is processed for storage in a dual memory structure comprising two first-in-first-out (FIFO) memories for storing 64 bit words, wherein the 64 bit word may be stored in one, or both, of the FIFOs. The SPI-4.2 receiver issues commands that control subsequent processing of the 64 bit words (e.g., for alignment) using three types of commands, which are based on the relative temporal position of control words in the received data. Temporally, these commands are characterized as: PRE-COMMANDS, POST-COMMANDS and PRESENT-COMMANDS. A parallel general and selection method (PGSM) is used for FIFO Write Command Generation and for Diagonally Interleaved Parity (DIP-4) checking.
摘要翻译：系统分组接口（SPI）4级接收机将四个连续的16位控制/数据字组合成单个64位字（合成速率高达210 MHz）。处理64位字以存储在双存储器结构中，包括两个用于存储64位字的先进先出（FIFO）存储器，其中64位字可以存储在FIFO中的一个或两者中。 SPI-4.2接收机发出使用三种类型的命令来控制64位字的后续处理（例如，用于对准）的命令，这些命令基于接收数据中的控制字的相对时间位置。这些命令暂时表征为：PRE-COMMANDS，POST-COMMANDS和PRESENT-COMMANDS。用于FIFO写入命令生成和对角线交错奇偶校验（DIP-4）检查的并行通用和选择方法（PGSM）。

3. 发明申请

US20080291917A1 System and method for designing and implementing packet processing products 有权
标题翻译：数据包处理产品的设计与实现方法
公开(公告)号：US20080291917A1
公开(公告)日：2008-11-27
申请号：US11805702
申请日：2007-05-24
申请人： Vispi Cassod , Anthony Dalleggio , Amine Kandalaft
发明人： Vispi Cassod , Anthony Dalleggio , Amine Kandalaft
IPC分类号： H04L12/56
CPC分类号： H04L41/22 , H04L41/0843 , H04L41/0879 , H04L49/10 , H04L49/30 , H04L49/3009
摘要： A system and method for allowing a user to create instructions for building a packet processing integrated circuit. The system includes a user interface for allowing a user to define a desired packet processing algorithm (4) using a plurality of discrete packet processing blocks (22, 24, 28, 30), each of the blocks corresponding to a portion of the desired packet processing algorithm (4). The system allows the user to define connections (10) between the plurality of packet processing blocks (22, 24, 28, 30). The system processes a plurality of packet processing blocks (22, 24, 28, 30) and the connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing the desired packet processing algorithm (19). The list of instructions can be delivered to a customer (12), or the customer can receive an integrated circuit constructed using the list of instructions (19), or the customer can receive a NETLIST generated using said list of instructions (16). The plurality of packet processing blocks (22, 24, 28, 30) can include a Packet Processing Unit (PPU, PPUX) 22, a Packet Modification Unit (PMU) 28, and a Decision and Forwarding Unit (DFU) 30.
摘要翻译：一种用于允许用户创建用于构建分组处理集成电路的指令的系统和方法。该系统包括用户界面，用于允许用户使用多个离散分组处理块（22,24,28,30）定义所需的分组处理算法（4），每个块对应于期望分组的一部分处理算法（4）。系统允许用户在多个分组处理块（22,24,28,30）之间定义连接（10）。系统处理多个分组处理块（22,24,28,30）和连接以提供用于产生能够执行所需分组处理算法（19）的集成电路的硬件描述语言中的指令列表。指令列表可以传递给客户（12），或者客户可以接收使用指令列表（19）构建的集成电路，或者客户可以接收使用所述指令列表（16）生成的NETLIST。多个分组处理块（22,24,28,30）可以包括分组处理单元（PPU，PPUX）22，分组修改单元（PMU）28以及决策和转发单元（DFU）30。

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