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1. 发明申请

US20110140743A1 Digital Frequency Generator 审中-公开
标题翻译：数字频率发生器
公开(公告)号：US20110140743A1
公开(公告)日：2011-06-16
申请号：US12683137
申请日：2010-01-06
申请人： Andrew Martin Mallinson
发明人： Andrew Martin Mallinson
IPC分类号： H03B21/00 , G06G7/16
CPC分类号： G06F1/025
摘要： A digital frequency generator is described.
摘要翻译：描述数字频率发生器。

2. 发明授权

US07028070B2 High speed filter 有权
公开(公告)号：US07028070B2
公开(公告)日：2006-04-11
申请号：US10057087
申请日：2002-01-26
申请人： Andrew Martin Mallinson
发明人： Andrew Martin Mallinson
IPC分类号： G06G1/02
CPC分类号： H03H15/00 , G06G7/1928
摘要： An electronic filter operates as a correlator that provides a discrete approximation of an analog signal. The analog to digital conversion is integrated directly approximation calculation. An array of sample and hold circuits or single bit comparators provide outputs to a series of multipliers, the other input of which is a coefficient value of a Fourier series approximation of the desired frequency response. Each of the sample and hold circuits samples sequentially in time and holds its sample until the next cycle. Thus the sample point rotates in time through the array and each new sample is multiplied by a different coefficient. The output of the multipliers is summed for evaluation.

3. 发明授权

US06646585B2 Flash analog-to-digital converter 失效
标题翻译：闪存模数转换器
公开(公告)号：US06646585B2
公开(公告)日：2003-11-11
申请号：US10118224
申请日：2002-04-05
申请人： Andrew Martin Mallinson
发明人： Andrew Martin Mallinson
IPC分类号： H03M136
CPC分类号： H03M1/367
摘要： A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.
摘要翻译：一种差分输入闪存模数转换器，其中连接比较器阵列以比较通过在阻抗网络上施加差分输入信号产生的这种信号的抛物面分布中的参考信号。优选地，比较器阵列包括至少两个多个比较器，第一多个比较器比较由第一步长分隔的参考节点对，而第二多个比较器比较由第二步长分隔的参考节点对。甚至更优选地，比较器阵列还包括第三多个比较器，其将由第三步长分隔的参考节点对进行比较，但仅在必要时使转换器的可用比较范围最大化。根据本发明的闪存转换器从输入提供增加的增益，而不会累积比较器输入电流，并且不牺牲参考信号的实际比较的数量。

4. 发明申请

US20080005215A1 System and method for reducing click using signal averaging on a high order modulator output 审中-公开
标题翻译：用于在高阶调制器输出上使用信号平均来减少点击的系统和方法
公开(公告)号：US20080005215A1
公开(公告)日：2008-01-03
申请号：US11479410
申请日：2006-06-30
申请人： Andrew Martin Mallinson , Dustin Forman
发明人： Andrew Martin Mallinson , Dustin Forman
IPC分类号： G06F17/10
CPC分类号： H03F3/217 , H03F1/305
摘要： The invention has been described in the context of a system and method of removing artifacts from an audio signal during shutdown of the output. The system includes a means by which the average value may be found to be zero or sufficiently close to zero as determined by the resolution of the filter output and a means by which the filter average value being zero or close to zero is used to disconnect (or equivalently change impedance or power) of the device or devices rendering the PWM signal into the analog domain as may be implemented by a Class D bridge chip and disconnection means.
摘要翻译：已经在关于输出关闭期间从音频信号中去除伪影的系统和方法的上下文中描述了本发明。该系统包括通过滤波器输出的分辨率确定的平均值可以被发现为零或足够接近零的装置，并且使用滤波器平均值为零或接近零的装置来断开（或等效地改变阻抗或功率），使得将PWM信号转换成可由D类桥芯片和断开装置实现的模拟域。

5. 发明授权

US06954165B2 Voltage segmented digital to analog converter 失效
标题翻译：电压分段数模转换器
公开(公告)号：US06954165B2
公开(公告)日：2005-10-11
申请号：US10810310
申请日：2004-03-26
申请人： Andrew Martin Mallinson
发明人： Andrew Martin Mallinson
IPC分类号： H03M20060101 , H03M1/00 , H03M1/06 , H03M1/12 , H03M1/66 , H03M1/68 , H03M1/76 , H03M1/78
CPC分类号： H03M1/0604 , H03M1/682 , H03M1/765
摘要： An improved segmented digital to analog converter is provided, configured with a novel method of compensating current flow in secondary or successive segmented elements. In operation, dual current devices initially load, then subsequently unload a cascade of resistor networks connected to the secondary or successive voltage segmenting elements, preventing the perturbation of precise operation of the primary or preceding elements. In contrast to conventional approaches, the improved converter obviates the need for a buffer or amplifier to isolate the secondary and successive voltage segmenting elements from the primary or preceding elements. In further contrast to conventional devices, a second and third successive voltage segmenting elements, where a third segmented series of resistors has a third set of resistors connected end to end from along which an output can be generated at any point between the resistors, wherein the third segmented series of resistors further includes one current source connected at one end of the third series of resistors, and a second current source connected at another end of the third series of resistors.
摘要翻译：提供了一种改进的分段数模转换器，其配置有补偿次级或连续分段元件中的电流的新颖方法。在操作中，双电流装置最初加载，随后卸载连接到次级或连续电压分段元件的级联的电阻网络，以防止主要或先前元件的精确操作的扰动。与常规方法相比，改进的转换器不需要缓冲器或放大器来隔离次级和连续的电压分段元件与初级元件或先前元件。与传统器件相反，第二和第三连续的电压分段元件，其中第三分段串联的电阻器具有端到端连接的第三组电阻器，沿着该电阻器可以在电阻器之间的任何点产生输出，其中，第三分段电阻器系列还包括连接在第三系列电阻器的一端的一个电流源和连接在第三系列电阻器的另一端的第二电流源。

6. 发明授权

US06897727B2 Current mode switch capacitor circuit 失效
标题翻译：电流模式开关电容电路
公开(公告)号：US06897727B2
公开(公告)日：2005-05-24
申请号：US10680811
申请日：2003-10-06
申请人： Andrew Martin Mallinson
发明人： Andrew Martin Mallinson
IPC分类号： H03F3/00 , H03F3/45
CPC分类号： H03F3/45094 , H03F3/005 , H03F2203/45461
摘要： A device is provided having at least two capacitive elements configured to retain a charge, and an interconnection of active devices between the capacitive elements. The active devices are configured to operate upon a transient charge flow as a current when in operation. The charge flow is partitioned into at least two capacitors according to the input voltage difference acting as a controlling parameter.
摘要翻译：提供了一种器件，其具有被配置为保持电荷的至少两个电容元件以及在电容元件之间的有源器件的互连。有源器件被配置为在瞬时充电流动时作为工作时的电流工作。根据作为控制参数的输入电压差，将电荷流分成至少两个电容器。

7. 发明授权

US06803871B2 Flash analog-to-digital converter 失效
标题翻译：闪存模数转换器
公开(公告)号：US06803871B2
公开(公告)日：2004-10-12
申请号：US10346034
申请日：2003-01-15
申请人： Andrew Martin Mallinson
发明人： Andrew Martin Mallinson
IPC分类号： H03M136
CPC分类号： H03M1/367
摘要： A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.
摘要翻译：一种差分输入闪存模数转换器，其中连接比较器阵列以比较通过在阻抗网络上施加差分输入信号产生的这种信号的抛物面分布中的参考信号。优选地，比较器阵列包括至少两个多个比较器，第一多个比较器比较由第一步长分隔的参考节点对，而第二多个比较器比较由第二步长分隔的参考节点对。甚至更优选地，比较器阵列还包括第三多个比较器，其将由第三步长分隔的参考节点对进行比较，但仅在必要时使转换器的可用比较范围最大化。根据本发明的闪存转换器从输入提供增加的增益，而不会累积比较器输入电流，并且不牺牲参考信号的实际比较的数量。

8. 发明授权

US08984035B2 Channel select filter apparatus and method 有权
标题翻译：通道选择滤波装置及方法
公开(公告)号：US08984035B2
公开(公告)日：2015-03-17
申请号：US13145748
申请日：2010-01-27
申请人： Andrew Martin Mallinson
发明人： Andrew Martin Mallinson
IPC分类号： G06J1/00 , G06G7/02 , B60N2/00
CPC分类号： H03H17/0248 , B60N2/002 , H03H15/00 , H03M1/687 , H03M1/745 , H03M1/747
摘要： Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital-to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.
摘要翻译：描述通道选择滤波器电路。一个电路实现了一个乘法元件和数 - 模转换器作为差分电流模式器件。实现乘法元件的另一个电路和具有加权相加的数模转换器，在数模转换器和乘法器组合的乘法之后延迟。在一个这样的电路中，基本相等的电流源幅度在电路的不同列中。另一个具有基本上相等的电流源幅度的这种电路使用非基数2。具有基本相等的电流源幅度的另一个这样的电路具有部分分割。另一电路实现了乘法元件和数模转换器，具有部分分段，元件的加扰位分配。如这里所述，一个这样的电路对等加权的片段进行比特分配。另一个电路实现了具有选择性地启用重复的电流源装置的乘法元件和数模转换器。另一电路实现了具有可变有效长度的数模转换器的乘法元件和数 - 模转换器。在一个这样的电路中，如本文所述，乘法器元件的一个或多个电流源被取消选择以去除乘法器元件的噪声贡献。复合滤波器电路包括一对实际有限脉冲响应滤波器电路，其在当前域中执行加法和减法，共享公共电阻网络以执行加权相加。一个这样的电路还包括第二对实际有限脉冲响应滤波器电路，其在当前域中执行加法和减法，共享第二公共电阻网络以执行加权相加。

9. 发明申请

US20110140738A1 Multi-Phase Integrators in Control Systems 审中-公开
标题翻译：控制系统中的多相积分器
公开(公告)号：US20110140738A1
公开(公告)日：2011-06-16
申请号：US12683162
申请日：2010-01-06
申请人： Andrew Martin Mallinson
发明人： Andrew Martin Mallinson
IPC分类号： G05B6/02 , H03L7/085 , G05B13/02
CPC分类号： G05B11/40 , H03F3/45183 , H03F2203/45166 , H03F2203/45224 , H03F2203/45674 , H03K3/0315 , H03L7/093 , H03L7/0995
摘要： Multi-phase integrators in control systems are described.
摘要翻译：描述了控制系统中的多相积分器。

10. 发明授权

US07782129B2 System and method to reduce audio artifacts from an audio signal by reducing the order of the control loop 有权
标题翻译：通过减少控制循环的顺序来减少音频信号的音频伪像的系统和方法
公开(公告)号：US07782129B2
公开(公告)日：2010-08-24
申请号：US11479394
申请日：2006-06-30
申请人： Andrew Martin Mallinson , Dustin Forman
发明人： Andrew Martin Mallinson , Dustin Forman
IPC分类号： H03F3/38 , H03F3/217 , H03F3/00
CPC分类号： H03F3/217 , H03F1/305
摘要： A system is provided for use in an audio signal processor to reduce the order of the loop to remove sound artifacts from an audio signal that includes an input for receiving an audio input signal a control loop of order greater than one configured to process the audio input signal and to output a Pulse Width Modulated audio output signal, a circuit for performing a gradual reduction of the order of the control loop such that prior to entering a shut down state the order is reduced to a single order and a circuit to disconnect a Driver Circuit from the Pulse Width modulated signal operated by a timing device designed to switch at the moment of zero average output value.
摘要翻译：提供了一种在音频信号处理器中使用的系统，以减少环路的顺序以消除音频信号中的声音伪像，该音频信号包括用于接收音频输入信号的输入，大于一个被配置为处理音频输入信号并输出脉冲宽度调制音频输出信号，用于执行逐渐降低控制回路的次序的电路，使得在进入关闭状态之前，该顺序被减少到单个顺序，并且电路断开驱动器来自脉冲宽度调制信号的电路由设计为在零平均输出值的时刻切换的定时装置操作。

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