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1. 发明授权

US07266728B1 Circuit for monitoring information on an interconnect 有权
标题翻译：用于监控互连信息的电路
公开(公告)号：US07266728B1
公开(公告)日：2007-09-04
申请号：US09410646
申请日：1999-10-01
申请人： David A. Edwards , Andrew M. Jones , John A. Carey , Anthony W. Rich
发明人： David A. Edwards , Andrew M. Jones , John A. Carey , Anthony W. Rich
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/364 , G06F11/3648
摘要： A circuit for monitoring information put onto an interconnect by one or more modules, said circuit comprising circuitry for determining if the information on the interconnect matches one or more conditions; and circuitry for preventing a module from putting further information onto said interconnect if it is determined that information on the interconnect matches said one or more conditions.
摘要翻译：一种用于监视由一个或多个模块放在互连上的信息的电路，所述电路包括用于确定所述互连上的信息是否匹配一个或多个条件的电路; 以及用于如果确定互连上的信息匹配所述一个或多个条件，则用于防止模块将更多信息放入所述互连的电路。

2. 发明授权

US06349371B1 Circuit for storing information 有权
标题翻译：用于存储信息的电路
公开(公告)号：US06349371B1
公开(公告)日：2002-02-19
申请号：US09411800
申请日：1999-10-01
申请人： Bernard Ramanadin , David A. Edwards , Andrew M. Jones , John A. Carey , Anthony W. Rich
发明人： Bernard Ramanadin , David A. Edwards , Andrew M. Jones , John A. Carey , Anthony W. Rich
IPC分类号： G06F1200
CPC分类号： G06F11/364 , G06F11/3485
摘要： In a system comprising an interconnect and a plurality of modules connected to the interconnect, a circuit for controlling which of said modules is able to put information onto said interconnect, said circuit comprising a store which stores status information for each module, said status information defining if the respective module is permitted to put information on said interconnect.
摘要翻译：在包括连接到互连的互连和多个模块的系统中，用于控制所述模块中的哪一个能够将信息放置在所述互连上的电路，所述电路包括存储每个模块的状态信息的存储器，所述状态信息定义如果允许相应的模块将信息放在所述互连上。

3. 发明授权

US06763034B1 Connection ports for interconnecting modules in an integrated circuit 有权
标题翻译：用于在集成电路中互连模块的连接端口
公开(公告)号：US06763034B1
公开(公告)日：2004-07-13
申请号：US09411828
申请日：1999-10-01
申请人： Andrew M. Jones , John A. Carey , Atsushi Hasegawa
发明人： Andrew M. Jones , John A. Carey , Atsushi Hasegawa
IPC分类号： H04L1266
CPC分类号： H04L49/102 , G06F15/7825 , H04L49/555
摘要： Connection ports for interconnecting functional modules in an integrated circuit are described. The connection ports provide enhanced functionality based around a common port primitive. This simplifies port design and selection and also allows a common packet protocol to be used for communication of packets across the packet router. In particular, there is improved functionality of target ports which allow out of order requests to be dealt with and out of order responses to be generated.
摘要翻译：描述用于在集成电路中互连功能模块的连接端口。连接端口基于公共端口原语提供增强的功能。这简化了端口设计和选择，并且还允许通用分组协议用于通过分组路由器的分组通信。特别地，改进了目标端口的功能，这些端口允许处理不及时的请求并产生无序响应。

4. 发明授权

US06298394B1 System and method for capturing information on an interconnect in an integrated circuit 有权
标题翻译：用于在集成电路中的互连上捕获信息的系统和方法
公开(公告)号：US06298394B1
公开(公告)日：2001-10-02
申请号：US09411617
申请日：1999-10-01
申请人： David A. Edwards , Andrew M. Jones , Anthony W. Rich
发明人： David A. Edwards , Andrew M. Jones , Anthony W. Rich
IPC分类号： G06F300
CPC分类号： G06F11/221
摘要： A circuit for use in a system comprising a plurality of modules connected to an interconnect, said modules being arranged to put information onto said interconnect, said circuit comprising circuitry for determining if information on the interconnect satisfies one or more conditions; and circuitry for storing at least part of the information which satisfies the one or more conditions.
摘要翻译：一种用于系统的电路，包括连接到互连的多个模块，所述模块被布置成将信息放置在所述互连上，所述电路包括用于确定所述互连上的信息是否满足一个或多个条件的电路; 以及用于存储满足一个或多个条件的信息的至少一部分的电路。

5. 发明授权

US09106055B2 Gas filled hollow fiber laser 有权
标题翻译：充气中空纤维激光
公开(公告)号：US09106055B2
公开(公告)日：2015-08-11
申请号：US13574550
申请日：2011-01-21
申请人： Wolfgang G. Rudolph , Amarin Ratanavis , Vasudevan Nampoothiri , Kristan L. Corwin , Andrew M. Jones , Brian R. Washburn , Rajesh Kadel , John M. Zavada
发明人： Wolfgang G. Rudolph , Amarin Ratanavis , Vasudevan Nampoothiri , Kristan L. Corwin , Andrew M. Jones , Brian R. Washburn , Rajesh Kadel , John M. Zavada
IPC分类号： H01S3/30 , H01S3/223 , H01S3/067 , H01S3/094 , H01S3/0943
CPC分类号： H01S3/223 , H01S3/06741 , H01S3/094003 , H01S3/0943 , H01S3/2232
摘要： Apparatus, systems, and methods using an optically pumped gas filled hollow fiber laser can be implemented in a variety of applications. In various embodiments, operation of an optically pumped gas filled hollow fiber laser is based on population inversion in the gas. Additional apparatus, systems, and methods are disclosed.
摘要翻译：使用光泵浦气体填充中空纤维激光器的装置，系统和方法可以在各种应用中实现。在各种实施例中，光泵浦气体填充中空纤维激光器的操作基于气体中的群体反转。公开了附加装置，系统和方法。

6. 发明授权

US07346072B2 Arbitration mechanism for packet transmission 有权
标题翻译：分组传输的仲裁机制
公开(公告)号：US07346072B2
公开(公告)日：2008-03-18
申请号：US10780355
申请日：2004-02-17
申请人： Andrew M. Jones , John A. Carey
发明人： Andrew M. Jones , John A. Carey
IPC分类号： H04L12/43
CPC分类号： H04L45/00
摘要： A pipelined arbitration mechanism allows a routing control decision to be effected for a later packet while a current packet is being transferred. The later packet can be issued a fixed number of cycles after the current request. The mechanism has particular advantages when used with a plurality of functional modules connected to a packet router, whereby a single functional module can generate a current request relating to a current packet and a deferred arbitration request relating to a later packet to be issued a fixed number of cycles after the current request.
摘要翻译：流水线仲裁机制允许在当前分组正在传输时对稍后的分组进行路由控制决定。稍后的数据包可以在当前请求之后发出固定数量的周期。当与连接到分组路由器的多个功能模块一起使用时，该机制具有特别的优点，由此单个功能模块可以生成与当前分组有关的当前请求以及与要发布固定数量的稍后分组有关的延迟仲裁请求的当前请求后的周期。

7. 发明授权

US07260745B1 Detection of information on an interconnect 有权
标题翻译：检测互连上的信息
公开(公告)号：US07260745B1
公开(公告)日：2007-08-21
申请号：US09410642
申请日：1999-10-01
申请人： David A. Edwards , Andrew M. Jones , Anthony W. Rich
发明人： David A. Edwards , Andrew M. Jones , Anthony W. Rich
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/364 , G06F11/3648
摘要： In a system comprising an interconnect and a plurality of modules connected to said interconnect for putting information onto the interconnect, a circuit comprising circuitry for receiving at least part of said of said information; circuitry for determining if said at least part of said information satisfies one or more conditions; and circuitry for performing one or more actions in response to the determination that at least part of the information satisfies one or more conditions.
摘要翻译：在包括互连和连接到所述互连以将信息放置到互连上的多个模块的系统中，包括用于接收所述信息的至少一部分的电路的电路; 用于确定所述信息的至少一部分是否满足一个或多个条件的电路; 以及用于响应于至少部分信息满足一个或多个条件的确定而执行一个或多个动作的电路。

8. 发明授权

US07228389B2 System and method for maintaining cache coherency in a shared memory system 有权
标题翻译：用于在共享存储器系统中维持高速缓存一致性的系统和方法
公开(公告)号：US07228389B2
公开(公告)日：2007-06-05
申请号：US11313261
申请日：2005-12-20
申请人： Andrew M. Jones , John Carrey
发明人： Andrew M. Jones , John Carrey
IPC分类号： G06F12/00
CPC分类号： G06F12/0833
摘要： A data processing system having shared memory accessible through a transaction-based bus mechanism. A plurality of system components, including a central processor, are coupled to the bus mechanism. The bus mechanism includes a cache coherency transaction within its transaction set. The cache coherency transaction comprises a request issued by one of the system components that is recognized by a cache unit of the central processor as an explicit command to perform a cache coherency operation. The transaction further comprises a response issued by the central processor indicating status of the cache coherency operation.
摘要翻译：具有通过基于事务的总线机制可访问的共享存储器的数据处理系统。包括中央处理器的多个系统组件耦合到总线机构。总线机制包括其事务集中的高速缓存一致性事务。高速缓存一致性事务包括由中央处理器的高速缓存单元识别的系统组件之一发出的请求作为执行高速缓存一致性操作的显式命令。交易还包括由中央处理器发出的指示高速缓存一致性操作的状态的响应。

9. 发明授权

US07000078B1 System and method for maintaining cache coherency in a shared memory system 有权
标题翻译：用于在共享存储器系统中维持高速缓存一致性的系统和方法
公开(公告)号：US07000078B1
公开(公告)日：2006-02-14
申请号：US09410928
申请日：1999-10-01
申请人： Andrew M. Jones , John Carrey
发明人： Andrew M. Jones , John Carrey
IPC分类号： G06F12/00
CPC分类号： G06F12/0833
摘要： A data processing system having shared memory accessible through a transaction-based bus mechanism. A plurality of system components, including a central processor, are coupled to the bus mechanism. The bus mechanism includes a cache coherency transaction within its transaction set. The cache coherency transaction comprises a request issued by one of the system components that is recognized by a cache unit of the central processor as an explicit command to perform a cache coherency operation. The transaction further comprises a response issued by the central processor indicating status of the cache coherency operation.
摘要翻译：具有通过基于事务的总线机制可访问的共享存储器的数据处理系统。包括中央处理器的多个系统组件耦合到总线机构。总线机制包括其事务集中的高速缓存一致性事务。高速缓存一致性事务包括由中央处理器的高速缓存单元识别的系统组件之一发出的请求作为执行高速缓存一致性操作的显式命令。交易还包括由中央处理器发出的指示高速缓存一致性操作的状态的响应。

10. 发明授权

US06598177B1 Monitoring error conditions in an integrated circuit 有权
标题翻译：监控集成电路中的错误状况
公开(公告)号：US06598177B1
公开(公告)日：2003-07-22
申请号：US09411798
申请日：1999-10-01
申请人： Andrew M. Jones , William B. Barnes
发明人： Andrew M. Jones , William B. Barnes
IPC分类号： G06F1100
CPC分类号： G01R31/31705
摘要： The invention relates to monitoring error conditions in an integrated circuit. The integrated circuit has a packet router to which a plurality of functional modules are connected between which packets are transmitted. Each functional module is associated with an error monitoring register for monitoring error conditions. The error monitoring register contains a plurality of error flags which can be set when a particular error condition is detected. The invention particularly but not exclusively relates to the setting of communication error flags relating to errors in communication of the packet.
摘要翻译：本发明涉及监测集成电路中的错误状况。集成电路具有分组路由器，多个功能模块连接在该分组路由器之间，在其间传送分组。每个功能模块与用于监视错误状况的错误监控寄存器相关联。错误监视寄存器包含多个错误标志，当检测到特定的错误条件时可以设置该错误标志。本发明特别地但不排他地涉及与分组的通信中的错误相关的通信错误标志的设置。

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