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1. 发明授权

US08593221B1 Methods and circuits for common mode stability and bandwidth broadening in transistor amplifiers 有权
标题翻译：晶体管放大器共模稳定性和带宽拓宽的方法和电路
公开(公告)号：US08593221B1
公开(公告)日：2013-11-26
申请号：US13300500
申请日：2011-11-18
申请人： Liping Zhang , Thomas W. Krawczyk , Andrew J. Bonthron , David A. Rowe
发明人： Liping Zhang , Thomas W. Krawczyk , Andrew J. Bonthron , David A. Rowe
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F3/45484 , H03F2203/45244
摘要： Examples of circuits and methods are provided for common mode stability and bandwidth broadening. A current generator circuit may include a first and a second transistor. Each of the first and second transistors includes a first, second, and third terminal. The first and second transistors provide a first and a second output current at their corresponding third terminals. A first branch including a first resistor and a first capacitor coupled in series is coupled between the third terminal of the first transistor and the first terminal of the second transistor. A second branch including a second resistor and a second capacitor coupled in series is coupled between the third terminal of the second transistor and the first terminal of the first transistor. The first and the second branches are configured to enable the current generator circuit to provide the first and second currents with improved common mode stability.
摘要翻译：提供了电路和方法的示例，用于共模稳定性和带宽拓宽。电流发生器电路可以包括第一和第二晶体管。第一和第二晶体管中的每一个包括第一，第二和第三端子。第一和第二晶体管在其相应的第三端提供第一和第二输出电流。包括第一电阻器和串联耦合的第一电容器的第一支路耦合在第一晶体管的第三端子和第二晶体管的第一端子之间。包括串联耦合的第二电阻器和第二电容器的第二支路耦合在第二晶体管的第三端子和第一晶体管的第一端子之间。第一和第二分支被配置为使得电流发生器电路能够提供改善的共模稳定性的第一和第二电流。

2. 发明授权

US08367469B2 Chip-scale semiconductor die packaging method 有权
标题翻译：芯片级半导体芯片封装方法
公开(公告)号：US08367469B2
公开(公告)日：2013-02-05
申请号：US13347543
申请日：2012-01-10
申请人： Andrew J. Bonthron , Darren Jay Walworth
发明人： Andrew J. Bonthron , Darren Jay Walworth
IPC分类号： H01L21/00
CPC分类号： H01L21/50 , H01L23/04 , H01L23/055 , H01L23/13 , H01L23/3675 , H01L23/492 , H01L23/552 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L2224/05554 , H01L2224/16225 , H01L2224/16235 , H01L2224/2929 , H01L2224/29311 , H01L2224/29324 , H01L2224/29347 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06589 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/10329 , H01L2924/10335 , H01L2924/10338 , H01L2924/12041 , H01L2924/1305 , H01L2924/14 , H01L2924/1517 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/16152 , H01L2924/16196 , H01L2924/16251 , H01L2924/167 , H01L2924/16787 , H01L2924/1679 , H01L2924/19041 , H01L2924/3025 , H01L2924/00 , H01L2924/15153 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of packaging one or more semiconductor dies is provided. The method includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism.
摘要翻译：提供一种封装一个或多个半导体管芯的方法。该方法包括：提供具有电路表面和连接表面的第一管芯; 提供具有内表面和外表面的芯片级框架，所述芯片级框架具有在所述内表面中具有开口的阱区; 使用用于电和机械耦合的第一联接机构将第一模具耦合到阱区域的壁; 提供具有顶表面和底表面的基底; 通过第二耦合机构将芯片级框架的内表面与基板的顶表面联接，其中在第一模具的电路表面和基板的顶表面之间设置间隙; 使用第三耦合机构将散热器耦合到芯片级框架的外表面。

3. 发明申请

US20120115279A1 CHIP-SCALE SEMICONDUCTOR DIE PACKAGING METHOD 有权
标题翻译：芯片半导体封装方法
公开(公告)号：US20120115279A1
公开(公告)日：2012-05-10
申请号：US13347543
申请日：2012-01-10
申请人： Andrew J. BONTHRON , Darren Jay WALWORTH
发明人： Andrew J. BONTHRON , Darren Jay WALWORTH
IPC分类号： H01L21/50
CPC分类号： H01L21/50 , H01L23/04 , H01L23/055 , H01L23/13 , H01L23/3675 , H01L23/492 , H01L23/552 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L2224/05554 , H01L2224/16225 , H01L2224/16235 , H01L2224/2929 , H01L2224/29311 , H01L2224/29324 , H01L2224/29347 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06589 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/10329 , H01L2924/10335 , H01L2924/10338 , H01L2924/12041 , H01L2924/1305 , H01L2924/14 , H01L2924/1517 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/16152 , H01L2924/16196 , H01L2924/16251 , H01L2924/167 , H01L2924/16787 , H01L2924/1679 , H01L2924/19041 , H01L2924/3025 , H01L2924/00 , H01L2924/15153 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of packaging one or more semiconductor dies is provided. The method includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism.
摘要翻译：提供一种封装一个或多个半导体管芯的方法。该方法包括：提供具有电路表面和连接表面的第一管芯; 提供具有内表面和外表面的芯片级框架，所述芯片级框架具有在所述内表面中具有开口的阱区; 使用用于电和机械耦合的第一联接机构将第一模具耦合到阱区域的壁; 提供具有顶表面和底表面的基底; 通过第二耦合机构将芯片级框架的内表面与基板的顶表面联接，其中在第一模具的电路表面和基板的顶表面之间设置间隙; 使用第三耦合机构将散热器耦合到芯片级框架的外表面。

4. 发明授权

US08093714B2 Chip assembly with chip-scale packaging 有权
标题翻译：芯片组装采用芯片级封装
公开(公告)号：US08093714B2
公开(公告)日：2012-01-10
申请号：US12635677
申请日：2009-12-10
申请人： Andrew J. Bonthron , Darren Jay Walworth
发明人： Andrew J. Bonthron , Darren Jay Walworth
IPC分类号： H01L23/34
CPC分类号： H01L21/50 , H01L23/04 , H01L23/055 , H01L23/13 , H01L23/3675 , H01L23/492 , H01L23/552 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L2224/05554 , H01L2224/16225 , H01L2224/16235 , H01L2224/2929 , H01L2224/29311 , H01L2224/29324 , H01L2224/29347 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06589 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/10329 , H01L2924/10335 , H01L2924/10338 , H01L2924/12041 , H01L2924/1305 , H01L2924/14 , H01L2924/1517 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/16152 , H01L2924/16196 , H01L2924/16251 , H01L2924/167 , H01L2924/16787 , H01L2924/1679 , H01L2924/19041 , H01L2924/3025 , H01L2924/00 , H01L2924/15153 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip assembly may comprise a substrate having a top surface and a bottom surface. The chip assembly may comprise a first die having a circuit surface and a connecting surface, the circuit surface comprising one or more integrated circuits. The chip assembly may comprise a chip-scale frame having an inside surface, an outside surface, and a well region, the well region having an opening within the inside surface, the well region having a wall, the well region housing the first die, the first die attached to the wall by a first coupling mechanism, the inside surface coupled to the top surface of the substrate by a second coupling mechanism. The chip assembly may comprise a heat sink coupled to the outside surface of the chip-scale frame using a third coupling mechanism.
摘要翻译：芯片组件可以包括具有顶表面和底表面的基底。芯片组件可以包括具有电路表面和连接表面的第一裸片，该电路表面包括一个或多个集成电路。芯片组件可以包括具有内表面，外表面和阱区的芯片级框架，阱区在内表面内具有开口，阱区具有壁，阱区容纳第一裸片，所述第一模具通过第一联接机构附接到所述壁，所述内表面通过第二联接机构联接到所述基板的顶表面。芯片组件可以包括使用第三耦合机构耦合到芯片尺寸框架的外表面的散热器。

5. 发明申请

US20110140260A1 CHIP ASSEMBLY WITH CHIP-SCALE PACKAGING 有权
标题翻译：芯片组件与芯片尺寸包装
公开(公告)号：US20110140260A1
公开(公告)日：2011-06-16
申请号：US12635677
申请日：2009-12-10
申请人： Andrew J. Bonthron , Darren Jay Walworth
发明人： Andrew J. Bonthron , Darren Jay Walworth
IPC分类号： H01L23/488 , H01L23/34 , H01L23/04 , H01L21/60 , H01L21/50
CPC分类号： H01L21/50 , H01L23/04 , H01L23/055 , H01L23/13 , H01L23/3675 , H01L23/492 , H01L23/552 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L2224/05554 , H01L2224/16225 , H01L2224/16235 , H01L2224/2929 , H01L2224/29311 , H01L2224/29324 , H01L2224/29347 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06589 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/10329 , H01L2924/10335 , H01L2924/10338 , H01L2924/12041 , H01L2924/1305 , H01L2924/14 , H01L2924/1517 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/16152 , H01L2924/16196 , H01L2924/16251 , H01L2924/167 , H01L2924/16787 , H01L2924/1679 , H01L2924/19041 , H01L2924/3025 , H01L2924/00 , H01L2924/15153 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip assembly may comprise a substrate having a top surface and a bottom surface. The chip assembly may comprise a first die having a circuit surface and a connecting surface, the circuit surface comprising one or more integrated circuits. The chip assembly may comprise a chip-scale frame having an inside surface, an outside surface, and a well region, the well region having an opening within the inside surface, the well region having a wall, the well region housing the first die, the first die attached to the wall by a first coupling mechanism, the inside surface coupled to the top surface of the substrate by a second coupling mechanism. The chip assembly may comprise a heat sink coupled to the outside surface of the chip-scale frame using a third coupling mechanism.
摘要翻译：芯片组件可以包括具有顶表面和底表面的基底。芯片组件可以包括具有电路表面和连接表面的第一裸片，该电路表面包括一个或多个集成电路。芯片组件可以包括具有内表面，外表面和阱区的芯片级框架，阱区在内表面内具有开口，阱区具有壁，阱区容纳第一裸片，所述第一模具通过第一联接机构附接到所述壁，所述内表面通过第二联接机构联接到所述基板的顶表面。芯片组件可以包括使用第三耦合机构耦合到芯片尺寸框架的外表面的散热器。

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