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1. 发明授权

US08332798B2 Using synthesis to place macros 有权
标题翻译：使用合成放置宏
公开(公告)号：US08332798B2
公开(公告)日：2012-12-11
申请号：US13042794
申请日：2011-03-08
申请人： Amit Chandra , Muthukumaravelu Velayoudame
发明人： Amit Chandra , Muthukumaravelu Velayoudame
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5072
摘要： In one embodiment, a design methodology is described in which a functional description of each macro may be synthesized along with the other logic in a block. The resulting circuitry, including synthesized circuitry corresponding to each macro, may be placed within an area designated for the integrated circuit. The result may be analyzed, determining a location for the macro based on the location of the corresponding synthesized circuitry. For example, the geometric center of the synthesized circuitry may be located, and the geometric center of the custom circuitry associated with the macro may be placed at the same point as the geometric center of the synthesized circuitry. Because the macros are not placed in advance, the location of the macro may be controlled by other factors such as timing, space, wiring congestion, etc.
摘要翻译：在一个实施例中，描述了一种设计方法，其中每个宏的功能描述可以与块中的其他逻辑一起被合成。所得到的电路，包括对应于每个宏的合成电路，可以被放置在为集成电路指定的区域内。可以分析结果，基于对应的合成电路的位置确定宏的位置。例如，合成电路的几何中心可以被定位，并且与宏相关联的定制电路的几何中心可以被放置在与合成电路的几何中心相同的点上。由于宏没有提前放置，所以宏的位置可能受时间，空间，布线拥堵等其他因素的控制。

2. 发明申请

US20110296264A1 Scan Insertion Optimization Using Physical Information 失效
标题翻译：使用物理信息扫描插入优化
公开(公告)号：US20110296264A1
公开(公告)日：2011-12-01
申请号：US12788983
申请日：2010-05-27
申请人： Amit Chandra , Muthukumaravelu Velayoudame , Mandeep Singh , Michael Mar
发明人： Amit Chandra , Muthukumaravelu Velayoudame , Mandeep Singh , Michael Mar
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318583
摘要： In an embodiment, a design methodology and tools to implement the methodology are used to perform scan insertion in an integrated circuit design. The physical location of the scan chains within the boundaries of the integrated circuit may be determined, and the methodology may use the physical information to perform the scan insertion. For example, the physical information may include the location of the inputs and outputs of the scan chains, as well as routability data indicating the ability to insert interconnect in the integrated circuit to make the desired scan connections. The location and routability information may be used to group scan chain inputs and outputs for, e.g., compression/decompression logic. Using physical data to insert scan compression/decompression logic may reduce the amount of area occupied by the scan logic and connectivity, in some embodiments.
摘要翻译：在一个实施例中，用于实现该方法的设计方法和工具用于在集成电路设计中执行扫描插入。可以确定扫描链在集成电路的边界内的物理位置，并且该方法可以使用物理信息来执行扫描插入。例如，物理信息可以包括扫描链的输入和输出的位置，以及指示在集成电路中插入互连以进行期望的扫描连接的能力的可路由数据。位置和可路由性信息可用于对例如压缩/解压缩逻辑的扫描链输入和输出进行分组。在一些实施例中，使用物理数据插入扫描压缩/解压缩逻辑可以减少扫描逻辑和连接所占用的面积的量。

3. 发明授权

US08332699B2 Scan insertion optimization using physical information 失效
标题翻译：使用物理信息扫描插入优化
公开(公告)号：US08332699B2
公开(公告)日：2012-12-11
申请号：US12788983
申请日：2010-05-27
申请人： Amit Chandra , Muthukumaravelu Velayoudame , Mandeep Singh , Michael Mar
发明人： Amit Chandra , Muthukumaravelu Velayoudame , Mandeep Singh , Michael Mar
IPC分类号： G01R31/28
CPC分类号： G01R31/318583
摘要： In an embodiment, a design methodology and tools to implement the methodology are used to perform scan insertion in an integrated circuit design. The physical location of the scan chains within the boundaries of the integrated circuit may be determined, and the methodology may use the physical information to perform the scan insertion. For example, the physical information may include the location of the inputs and outputs of the scan chains, as well as routability data indicating the ability to insert interconnect in the integrated circuit to make the desired scan connections. The location and routability information may be used to group scan chain inputs and outputs for, e.g., compression/decompression logic. Using physical data to insert scan compression/decompression logic may reduce the amount of area occupied by the scan logic and connectivity, in some embodiments.
摘要翻译：在一个实施例中，用于实现该方法的设计方法和工具用于在集成电路设计中执行扫描插入。可以确定扫描链在集成电路的边界内的物理位置，并且该方法可以使用物理信息来执行扫描插入。例如，物理信息可以包括扫描链的输入和输出的位置，以及指示在集成电路中插入互连以进行期望的扫描连接的能力的可路由数据。位置和可路由性信息可用于对例如压缩/解压缩逻辑的扫描链输入和输出进行分组。在一些实施例中，使用物理数据插入扫描压缩/解压缩逻辑可以减少扫描逻辑和连接所占用的面积的量。

4. 发明申请

US20120233577A1 Using Synthesis to Place Macros 有权
标题翻译：使用合成放置宏
公开(公告)号：US20120233577A1
公开(公告)日：2012-09-13
申请号：US13042794
申请日：2011-03-08
申请人： Amit Chandra , Muthukumaravelu Velayoudame
发明人： Amit Chandra , Muthukumaravelu Velayoudame
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5072
摘要： In one embodiment, a design methodology is described in which a functional description of each macro may be synthesized along with the other logic in a block. The resulting circuitry, including synthesized circuitry corresponding to each macro, may be placed within an area designated for the integrated circuit. The result may be analyzed, determining a location for the macro based on the location of the corresponding synthesized circuitry. For example, the geometric center of the synthesized circuitry may be located, and the geometric center of the custom circuitry associated with the macro may be placed at the same point as the geometric center of the synthesized circuitry. Because the macros are not placed in advance, the location of the macro may be controlled by other factors such as timing, space, wiring congestion, etc.
摘要翻译：在一个实施例中，描述了一种设计方法，其中每个宏的功能描述可以与块中的其他逻辑一起被合成。所得到的电路，包括对应于每个宏的合成电路，可以被放置在为集成电路指定的区域内。可以分析结果，基于对应的合成电路的位置确定宏的位置。例如，合成电路的几何中心可以被定位，并且与宏相关联的定制电路的几何中心可以被放置在与合成电路的几何中心相同的点上。由于宏没有提前放置，所以宏的位置可能受时间，空间，布线拥堵等其他因素的控制。

5. 发明申请

US20120303395A1 Relationship Assessment 审中-公开
标题翻译：关系评估
公开(公告)号：US20120303395A1
公开(公告)日：2012-11-29
申请号：US13113154
申请日：2011-05-23
申请人： Ankit Saxena , Viral Chhaya , Amit Chandra
发明人： Ankit Saxena , Viral Chhaya , Amit Chandra
IPC分类号： G06Q10/00
CPC分类号： G06Q10/0637
摘要： Systems and methods of evaluating and/or assessing the health of a relationship are provided. In some examples, the systems and methods may include identifying a first party and a second party in a relationship. The systems and methods may further include determining a plurality of parameters for evaluation. In some examples, a first portion of the parameters may be evaluated based on what the second party thinks of the first party from a business engagement perspective. Another portion of the parameters may be evaluated based on how well prepared the first party is to meet the business needs of the second party. The scores may be combined to determine an overall health of the relationship and, in some examples, the results may be represented graphically and/or using color to indicate the health of the relationship.
摘要翻译：提供了评估和/或评估关系健康的系统和方法。在一些示例中，系统和方法可以包括识别关系中的第一方和第二方。系统和方法还可以包括确定用于评估的多个参数。在一些示例中，参数的第一部分可以基于第二方从业务参与角度来看第一方的意见来评估。参数的另一部分可以基于第一方如何准备好满足第二方的业务需求进行评估。分数可以组合以确定关系的总体健康状况，并且在一些示例中，结果可以用图形化和/或使用颜色来表示关系的健康。

6. 发明授权

US06449899B1 Method for inducing improved seed germination in Podophyllum hexandrum Royle 失效
标题翻译：在茯苓中提取种子发芽的方法
公开(公告)号：US06449899B1
公开(公告)日：2002-09-17
申请号：US09800672
申请日：2001-03-08
申请人： Amit Chandra Kharkwal , Om Prakash , Amita Bhattacharya , Pramod Kumar Nagar , Paramvir Singh Ahuja
发明人： Amit Chandra Kharkwal , Om Prakash , Amita Bhattacharya , Pramod Kumar Nagar , Paramvir Singh Ahuja
IPC分类号： A01G100
CPC分类号： A01C1/02 , A01H4/005
摘要： The present invention describes a method for inducing improved seed germination in a high altitude medicinal plant, Podophyllum hexandrum Royle through hot water treatment at 40° C.-100° C. for 30-120 seconds.
摘要翻译：本发明描述了一种通过在40℃-100℃下热水处理30-120秒，在高空药用植物茯苓中加入种子发芽的方法。

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