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1. 发明授权

US07372290B2 System and method for using dummy cycles to mask operations in a secure microcontroller 有权
标题翻译：使用虚拟周期来屏蔽安全微控制器中的操作的系统和方法
公开(公告)号：US07372290B2
公开(公告)日：2008-05-13
申请号：US11243329
申请日：2005-10-04
申请人： Serge F. Fruhauf , Alain C. Pomet
发明人： Serge F. Fruhauf , Alain C. Pomet
IPC分类号： H03K19/00
CPC分类号： H04L9/003 , G06F21/755 , G06F21/77 , G06F2221/2123 , H04L2209/046 , H04L2209/08 , H04L2209/12
摘要： A secure device includes a memory capable of storing information. The secure device also includes a secure microcontroller capable of securing the information in the memory. The secure microcontroller includes a plurality of registers. The secure microcontroller also includes combinatorial logic capable of receiving at least one output value provided by at least one of the registers. The combinatorial logic is also capable of performing one or more combinatorial operations using the at least one received output value. In addition, the secure microcontroller includes dummy cycle circuitry capable of causing one or more of the registers and the combinatorial logic to change state and consume current during one or more dummy cycles.
摘要翻译：安全装置包括能够存储信息的存储器。安全装置还包括能够将信息保护在存储器中的安全微控制器。安全微控制器包括多个寄存器。安全微控制器还包括能够接收由至少一个寄存器提供的至少一个输出值的组合逻辑。组合逻辑还能够使用至少一个接收到的输出值来执行一个或多个组合操作。此外，安全微控制器包括能够使一个或多个寄存器和组合逻辑在一个或多个虚拟周期期间改变状态并消耗电流的虚拟周期电路。

2. 发明授权

US07372304B2 System and method for glitch detection in a secure microcontroller 有权
标题翻译：安全微控制器中毛刺检测的系统和方法
公开(公告)号：US07372304B2
公开(公告)日：2008-05-13
申请号：US11243328
申请日：2005-10-04
申请人： Serge F. Fruhauf , Alain C. Pomet
发明人： Serge F. Fruhauf , Alain C. Pomet
IPC分类号： H03K19/00
CPC分类号： G01R31/31719 , G06K19/07309
摘要： An apparatus includes a plurality of macrocells formed from logic capable of performing one or more functions. The apparatus also includes a clock tree capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clock tree includes a local branch within each macrocell, where each local branch is capable of providing at least one copy of the clock signal. In addition, the apparatus includes at least one glitch detection circuit capable of detecting a glitch in one or more copies of the clock signal provided by the local branches in the macrocells.
摘要翻译：一种装置包括由能够执行一个或多个功能的逻辑形成的多个宏小区。该装置还包括能够接收时钟信号并且向每个宏小区提供时钟信号的至少一个副本的时钟树。时钟树包括每个宏小区内的本地分支，其中每个本地分支能够提供时钟信号的至少一个副本。此外，该装置包括至少一个毛刺检测电路，能够检测由宏单元中的本地分支提供的时钟信号的一个或多个拷贝中的毛刺。

3. 发明授权

US07181649B2 Universal serial bus (USB) smart card having enhanced testing features and related system, integrated circuit, and methods 有权
标题翻译：通用串行总线（USB）智能卡具有增强的测试功能和相关系统，集成电路和方法
公开(公告)号：US07181649B2
公开(公告)日：2007-02-20
申请号：US10434820
申请日：2003-05-09
申请人： Serge Fruhauf , Taylor J. Leaming , Alain C. Pomet
发明人： Serge Fruhauf , Taylor J. Leaming , Alain C. Pomet
IPC分类号： G06F11/00
CPC分类号： G06K7/10465 , G06K7/0008 , G06K7/0095 , G06K19/07 , G06K19/07733
摘要： An integrated circuit for a smart card may include a universal serial bus (USB) transceiver for communicating with a USB host device, and a microprocessor connected to the USB transceiver and operable in a test mode and a user mode. When in the test mode, the microprocessor may perform a test operation based upon receiving at least one test vendor specific request (VSR) from the USB host device via the at least one USB transceiver. By way of example, the test operation may include scan testing the microprocessor's control logic, detecting a status of at least one buffer and communicating the status to the USB host device, writing test data to at least one designated buffer and sending the test data from the at least one designated buffer to the USB host device, and/or operating with reduced power.
摘要翻译：用于智能卡的集成电路可以包括用于与USB主机设备通信的通用串行总线（USB）收发器和连接到USB收发器的微处理器，并且可以在测试模式和用户模式下操作。当处于测试模式时，微处理器可以经由至少一个USB收发器从USB主机设备接收至少一个测试供应商特定请求（VSR）来执行测试操作。作为示例，测试操作可以包括对微处理器的控制逻辑进行扫描测试，检测至少一个缓冲器的状态并将状态传送到USB主机设备，将测试数据写入至少一个指定的缓冲器，并将测试数据从所述至少一个指定的缓冲器到达所述USB主机设备，和/或以降低的功率运行。

4. 发明授权

US06343364B1 Method and device for local clock generation using universal serial bus downstream received signals DP and DM 有权
标题翻译：使用通用串行总线下行接收信号DP和DM的本地时钟生成方法和装置
公开(公告)号：US06343364B1
公开(公告)日：2002-01-29
申请号：US09614736
申请日：2000-07-13
申请人： Robert A. Leydier , Alain C. Pomet
发明人： Robert A. Leydier , Alain C. Pomet
IPC分类号： G06F104
CPC分类号： G06K19/07733 , G06F1/04 , G06K7/0008 , G06K19/07 , H04L7/0331 , H04L7/0337 , H04L7/04 , H04L7/10
摘要： A method and device is disclosed for generating a local clock signal CLK1X (172) from Universal Synchronous Bus downstream-received differential signals DM and DP carrying the downstream received bit-serial signal. The method and device does not require the use of a crystal or resonator. Counters (312, 310, 305, 301) are used to determine a number of periods of a free-running high frequency clock signal (164) contained within in a known number of bit periods of the downstream received bit-serial signal (146). The counter values are divided by the known number of bit periods of the received bit-serial signal (146) to determine a bit period of the received bit-serial signal (146). The local clock signal (172) may be phase-locked with the received bit serial signal (146). The local clock period is updated on an ongoing manner by downstream known received traffic.
摘要翻译：公开了用于从承载下游接收的位串行信号的通用同步总线下游接收差分信号DM和DP产生本地时钟信号CLK1X（172）的方法和装置。该方法和装置不需要使用晶体或谐振器。计数器（312,310,305,301）用于确定包含在下游接收位串行信号（146）的已知数量的位周期内的自由运行的高频时钟信号（164）的周期数，。将计数器值除以接收到的位串行信号（146）的已知位数周期，以确定接收的位串行信号（146）的位周期。本地时钟信号（172）可以与所接收的位串行信号（146）锁相。本地时钟周期以下游已知的接收流量以持续的方式更新。

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