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1. 发明授权

US4891780A Divisional operation system for obtaining a quotient by repeated subtraction and shift operations 失效
标题翻译：通过重复减法和换档操作获得商的分割操作系统
公开(公告)号：US4891780A
公开(公告)日：1990-01-02
申请号：US167173
申请日：1988-03-11
申请人： Akio Miyoshi
发明人： Akio Miyoshi
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F2207/5352 , G06F7/4991
摘要： A divisional operation is performed by the invention, using three registers. The higher order digits or figures of dividend are given to the first register and the lower order digits or figures thereof are given to the second register. In addition, a divisor is given to the third register. Subtraction is performed between the content of the first register and the content of the third register. On the basis of the sign of the result, the quotient is determined. Every time subtraction is performed, a shift operation is conducted in the first and second registers. The quotient is stored in the second register from the least significant bit thereof. In such a shift operation, data of 1 bit is transferred from the most significant bit of the second register to the least significant bit of the first register. Where the data of 1 bit thus transferred represents "1" when the operation is completed, it is detected that division is in an overflow state.
摘要翻译：本发明使用三个寄存器执行分割操作。给予第一个寄存器的高阶数字或红利数字，并将低位数字或数字赋予第二寄存器。另外还有一个除数给第三个登记册。在第一寄存器的内容和第三寄存器的内容之间执行减法。在结果符号的基础上，确定商。执行每次减法时，在第一和第二寄存器中进行移位操作。商从其最低有效位存储在第二寄存器中。在这种移位操作中，1比特的数据从第二寄存器的最高有效位传送到第一寄存器的最低有效位。如果这样传送的1位的数据在操作完成时表示“1”，则检测到该划分处于溢出状态。

2. 发明授权

US4766538A Microprocessor having variable data width 失效
标题翻译：具有可变数据宽度的微处理器
公开(公告)号：US4766538A
公开(公告)日：1988-08-23
申请号：US807224
申请日：1985-12-10
申请人： Akio Miyoshi
发明人： Akio Miyoshi
IPC分类号： G06F13/36 , G06F12/06 , G06F13/40 , G06F15/78 , G06F13/00
CPC分类号： G06F13/4018 , G06F12/0607
摘要： A microprocessor having variable data width comprising a bus cycle changeover circuit between a command execution unit and each of an address output logic, a data input/output logic, and a bus controller. The bus cycle changeover circuit receives an address, data, a memory access instruction and a data width instruction from the command execution unit and modifies timings of them according to an externally supplied data width selection signal and transmits modified address, data, memory access instruction and data width instruction signals to the address output logic, the data input/output logic and the bus controller. The bus cycle changeover circuit comprises a cycle control circuit which outputs a signal expressing a latter half access cycle and an upper/lower selection circuit which selects upper/lower parts of the data bus according to an output signal of the cycle control circuit.
摘要翻译：具有可变数据宽度的微处理器包括命令执行单元与地址输出逻辑，数据输入/输出逻辑和总线控制器之间的总线周期切换电路。总线周期切换电路从命令执行单元接收地址，数据，存储器访问指令和数据宽度指令，并根据外部提供的数据宽度选择信号修改它们的定时，并发送修改的地址，数据，存储器存取指令和数据宽度指令信号到地址输出逻辑，数据输入/输出逻辑和总线控制器。总线周期切换电路包括输出表示后半存取周期的信号的周期控制电路和根据循环控制电路的输出信号选择数据总线的上/下部分的上/下选择电路。

3. 发明授权

US5053954A Microprogram process for single cycle jump instruction execution 失效
标题翻译：单周期跳转指令执行的微程序处理
公开(公告)号：US5053954A
公开(公告)日：1991-10-01
申请号：US620386
申请日：1990-11-30
申请人： Akio Miyoshi
发明人： Akio Miyoshi
IPC分类号： G06F9/32 , G06F9/22 , G06F9/26
CPC分类号： G06F9/264
摘要： A microprogram processor to execute high speed processing of macro instructions using microcodes is provided. This microprogram processor comprises a microcode decoder for decoding a microcode generated from a microprogram ROM in response to a macro instruction, and a jump judgement decoder responsive to a jump condition signal externally delivered and a result decoded by the microcode decoder, to generate a microjump signal when a jump condition holds. The microprogram processor further comprises a circuit for generating a next instruction start signal for immediately shifting to a next instruction on the basis of a decoded signal signifying the start of a next macro instruction when no request for a jump is outputted from the microcode decoder. Such a next instruction start signal generator circuit may be realized by a simple logic circuit. In addition, the jump judgement decoder further responds to data of a portion (e.g., a specific bit) of operation data in addition to the decoded result and the jump condition signal. Such a specific bit may be a MSB. Thus, the execution of the step for shifting data and examining a carry as the jump condition becomes unnecessary.
摘要翻译：提供了使用微码来执行宏指令的高速处理的微程序处理器。该微程序处理器包括微代码解码器，用于响应于宏指令对从微程序ROM生成的微代码进行解码，以及响应于外部传递的跳转条件信号和由微代码解码器解码的结果的跳转判断解码器，以产生微点击信号当跳转条件成立时。该微程序处理器还包括一个电路，用于当不从微码解码器输出跳跃请求时，基于表示下一个宏指令的开始的解码信号，产生下一个指令开始信号，以便立即转换到下一个指令。这样的下一个指令开始信号发生器电路可以由简单的逻辑电路来实现。此外，除了解码结果和跳转条件信号之外，跳转判断解码器还响应于操作数据的一部分（例如，特定比特）的数据。这样的特定位可以是MSB。因此，不需要执行用于移动数据和检查进位作为跳转条件的步骤。

4. 发明授权

US4439247A Method for manufacture of high-strength high-electroconductivity copper alloy 失效
标题翻译：高强度高导电铜合金的制造方法
公开(公告)号：US4439247A
公开(公告)日：1984-03-27
申请号：US443556
申请日：1982-11-22
申请人： Kishio Arita , Toshio Takahashi , Akio Miyoshi , Hajime Izumimori , Mitsushi Ishida
发明人： Kishio Arita , Toshio Takahashi , Akio Miyoshi , Hajime Izumimori , Mitsushi Ishida
IPC分类号： H01L23/48 , C22C9/00 , C22F1/00 , C22F1/08
CPC分类号： C22F1/08
摘要： A copper alloy which is high in strength and electroconductivity is manufactured by casting, without chill casting, a copper alloy mass substantially consisting of copper and containing 0.2 to 1.5% by weight of chromium and 0.01 to 0.5% by weight of tin, hot working the cast copper alloy mass, then cooling, not slowly, the hot worked alloy mass without being subjected to any solid solution treatment, further cold working the cooled alloy mass, and thereafter subjecting the cold worked alloy mass to an aging treatment.
摘要翻译：高强度和导电性的铜合金通过铸造而不是冷铸而制造，铜合金质量基本上由铜组成，含有0.2〜1.5重量％的铬和0.01〜0.5重量％的锡，热加工铸造铜合金质量，然后冷却，而不是缓慢地，热处理的合金质量不经过任何固溶处理，对冷却的合金块进行进一步的冷加工，然后对冷加工的合金质量进行时效处理。

5. 发明授权

US5636375A Emulator for high speed, continuous and discontinuous instruction fetches 失效
标题翻译：用于高速，连续和不连续指令读取的仿真器
公开(公告)号：US5636375A
公开(公告)日：1997-06-03
申请号：US619138
申请日：1996-03-20
申请人： Akio Miyoshi
发明人： Akio Miyoshi
IPC分类号： G06F9/32 , G06F9/318 , G06F9/38 , G06F9/455
CPC分类号： G06F9/3017 , G06F9/3802 , G06F9/45504
摘要： A jump judgment circuit judges whether an instruction read bus cycle of a CPU to be emulated is to be executed in a sequential order of addresses of a memory. A control circuit operates in accordance with the judgment result. Specifically, if an instruction is in the sequential order of addresses of a memory relative to the immediately preceding instruction, instruction codes previously read from the memory and converted are read from a queue and supplied to the CPU. If an instruction is not in the sequential order of addresses, which would correspond to a jump to a noncontiguous address of a memory, that instruction is read from the memory at the designated address, converted into instruction codes, and supplied to CPU.
摘要翻译：跳转判断电路判断要被仿真的CPU的指令读总线周期是按照存储器地址的顺序执行。控制电路根据判断结果进行动作。具体来说，如果指令是相对于紧接在前的指令的存储器的地址的顺序，则从存储器读取并转换的指令代码从队列读取并提供给CPU。如果指令不是地址的顺序，这对应于跳转到存储器的不连续地址，则该指令从指定地址的存储器读取，转换成指令代码，并提供给CPU。

6. 发明授权

US5295187A Illegal copy prevention apparatus 失效
标题翻译：非法防伪装置
公开(公告)号：US5295187A
公开(公告)日：1994-03-15
申请号：US801608
申请日：1991-12-05
申请人： Akio Miyoshi
发明人： Akio Miyoshi
IPC分类号： G06F12/14 , G06F1/00 , G06F21/00 , G06F21/22 , G06F21/24 , H01L27/02 , G11B23/28 , G05B9/02
CPC分类号： H01L27/02 , G06F21/121
摘要： An illegal copy prevention apparatus including a plurality of illegal copy discriminators (e.g. instructions to set flags), an event generator (e.g. detections of "0" sec in real time) corresponding to the illegal copy discriminators, and an abnormal operation generator for generating an abnormal operation when any one of the illegal discriminator and the corresponding event generator generates an event. Since the probability at which all the abnormal operations are generated by all the abnormal operation generators is low, it is extremely difficult for a violator to notice the presence of all the copy protections and further remove all the copy protections completely, thus realizing an effective illegal copy prevention apparatus for computer software and circuit configuration of IC devices.
摘要翻译：一种非法复制防止装置，包括多个非法复制鉴别器（例如设置标志的指令），与非法复制识别器相对应的事件发生器（例如实时检测“0”秒），以及异常运算发生器，当非法鉴别器和相应的事件发生器中的任何一个产生事件时，异常操作。由于所有异常操作发生器产生的所有异常操作的概率较低，违规者很难注意到存在所有复制保护，并进一步完全删除所有复制保护，从而实现有效的非法操作 IC设备的计算机软件和电路配置的防复制装置。

7. 发明授权

US5233695A Microprocessor with a reduced size microprogram 失效
标题翻译：具有缩小尺寸微程序的微处理器
公开(公告)号：US5233695A
公开(公告)日：1993-08-03
申请号：US552841
申请日：1990-07-16
申请人： Akio Miyoshi
发明人： Akio Miyoshi
IPC分类号： G06F9/22
CPC分类号： G06F9/223
摘要： When a data processing instruction is given to a microprocessor, and the code of a data register subject to designation is held in an instruction register, a first logic level is outputted from the instruction code decoder, but when the register subject to designation is the instruction queuing register in which a subsequent instruction code is to be held, a second logic level is outputted from the instruction code decoder. By the operation of logic switching means, when the first logic level is being outputted, the register select code decoder can select the data register designated, while when the second logic level is being outputted, the register select code decoder can select the instruction queuing register designated. Accordingly, this eliminates the necessity of carrying out the designation of a data register or queuing register in the microprogram, thus making it possible to reduce the size of the microprogram used.
摘要翻译：当向微处理器提供数据处理指令，并且将要指定的数据寄存器的代码保存在指令寄存器中时，从指令代码解码器输出第一逻辑电平，但是当要指定的寄存器是指令时其中将要保留后续指令代码的排队寄存器，从指令代码解码器输出第二逻辑电平。通过逻辑切换装置的操作，当输出第一逻辑电平时，寄存器选择码解码器可以选择指定的数据寄存器，而当输出第二逻辑电平时，寄存器选择码解码器可以选择指令排队寄存器指定因此，这消除了在微程序中执行数据寄存器或排队寄存器的指定的必要性，从而可以减小所使用的微程序的尺寸。

8. 发明授权

US5046040A Microprogram control apparatus using don't care bits as part of address bits for common instructions and generating variable control bits 失效
标题翻译：使用无关位的微程序控制装置作为公共指令的地址位的一部分并产生可变控制位
公开(公告)号：US5046040A
公开(公告)日：1991-09-03
申请号：US947642
申请日：1986-12-30
申请人： Akio Miyoshi
发明人： Akio Miyoshi
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/223 , G06F9/268
摘要： A microprogram control device comprises a machine instruction decoder (11) for sequentially decoding machine instructions fetched from an external computer memory and providing a microcode start address for each decoded instruction, a counter (12) connected to the decoder for generating a required number of microcode addresses, a microcode storage unit (13) comprising an address decoding area (13a) in which microcodes are designated by microcode address and a microcode memory area (13b) in which the microcodes associated with the machine instructions are stored, and a microcode register (14) for controlling the operation of circuits (25) to be controlled and for providing a control signal output (Sc) to the counter. A "don't care" function is associated with certain bit positions of microcode addresses of microsteps common to sequential machine instructions. In this manner memory chip area may be reduced without any decrease in microcomputer operating speed. Nevertheless, the embodiment may further provide for designation of branching operations via incorporation of a next microinstruction address determination circuit coupled between the machine instruction decoding circuit and the counter, the next microinstruction address determination circuit being controlled by a microcode decoding circuit coupled to the output of the microcode register.
摘要翻译：微程序控制装置包括：机器指令解码器，用于对从外部计算机存储器取出的机器指令进行顺序解码，并为每个解码指令提供微代码起始地址;连接到解码器的计数器，用于产生所需数量的微代码地址，微码存储单元（13），其包括微代码地址指定了微码的地址解码区（13a）和存储与机器指令相关联的微代码的微代码存储区（13b）和微代码寄存器（ 14），用于控制要被控制的电路（25）的操作并且用于向计数器提供控制信号输出（Sc）。 “无关”功能与顺序机器指令通用的微步的微码地址的某些位位置相关联。以这种方式，可以减少存储器芯片面积而没有微计算机操作速度的任何降低。然而，该实施例还可以通过结合耦合在机器指令解码电路和计数器之间的下一个微指令地址确定电路来指定分支操作，下一个微指令地址确定电路由耦合到微码寄存器。

9. 发明授权

US4640436A Hermetic sealing cover and a method of producing the same 失效
标题翻译：密封盖及其制造方法
公开(公告)号：US4640436A
公开(公告)日：1987-02-03
申请号：US836493
申请日：1986-03-05
申请人： Akio Miyoshi , Akira Fukami
发明人： Akio Miyoshi , Akira Fukami
IPC分类号： H01L23/02 , H01L23/04 , H01L23/10 , B65D41/00
CPC分类号： H01L23/10 , H01L2224/48091 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/01025 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/15153 , H01L2924/15165 , H01L2924/16195 , Y10T29/49171
摘要： A hermetic sealing cover assembly for a semiconductor device, etc. has a seal ring and a metallic cover joined thereto. The seal ring has a thin layer of gold, silver, platinum or palladium. The cover has a film of a material of high solderability, such as gold or nickel, formed at least on the peripheral edge of its surface facing the seal ring. The ring is joined in its entirety to the peripheral edge of the cover so that the layer on the ring may be bonded to the film on the cover. A method of producing such a sealing cover assembly is also disclosed.
摘要翻译：用于半导体装置等的密封盖组件具有密封环和与其连接的金属盖。密封圈有一层薄薄的金，银，铂或钯。该盖具有至少在其面向密封环的表面的周边边缘上形成的具有高可焊性的材料（例如金或镍）的膜。环整体连接到盖的周缘，使得环上的层可以结合到盖上的膜。还公开了一种制造这种密封盖组件的方法。

10. 发明授权

US06441670B1 5V-tolerant receiver for low voltage CMOS technologies 失效
标题翻译：用于低电压CMOS技术的5V耐受接收器
公开(公告)号：US06441670B1
公开(公告)日：2002-08-27
申请号：US09930413
申请日：2001-08-15
申请人： Terry C. Coughlin, Jr. , Joseph M. Milewski , Akio Miyoshi , Loc Khac Nguyen
发明人： Terry C. Coughlin, Jr. , Joseph M. Milewski , Akio Miyoshi , Loc Khac Nguyen
IPC分类号： H03K508
CPC分类号： H03K5/08 , H03K19/00315
摘要： Receiver circuit providing interface between a legacy system sourcing logic signals including high logic level signals at first voltage levels to semiconductor IC devices operating at second voltage levels, wherein the first voltage levels are greater than the second voltage levels. The receiver circuit comprises: a pass gate device receiving the input voltages including high level logic signals at first logic levels and translating the high logic level signals to an intermediate voltage level for output at a first circuit node, the intermediate voltage level being less than the first voltage level; a first inverter device for receiving the translated voltages at the intermediate voltage levels and inverting the voltages for output at a second circuit node, whereby high input logic level voltages are pulled down at the second node and low input logic level voltages are pulled up at the second node; a circuit element in series with the first inverter device for connecting the first inverter device to a voltage supply source that provides pulled up signals at the second voltage levels in response to low logic level input voltages; and, a circuit responsive to pulled down voltage at the second node for deactivating the first circuit element to thereby prevent leakage current to ground through the first inverter device. Stable switching of voltages is achieved at the second node in a manner that eliminates leakage current between the voltage supply source providing pulled up signals at the second voltage levels and the receiver input.
摘要翻译：接收器电路提供传统系统之间的接口，逻辑信号包括在第一电压电平处的高逻辑电平信号到在第二电压电平工作的半导体IC器件，其中第一电压电平大于第二电压电平。接收器电路包括：通过栅极器件，其接收包括处于第一逻辑电平的高电平逻辑信号的输入电压，并将高逻辑电平信号转换成中间电压电平以在第一电路节点处输出，所述中间电压电平小于第一电压电平; 第一逆变器装置，用于接收处于中间电压电平的转换电压并使第二电路节点处的输出电压反相，从而在第二节点向下拉高输入逻辑电平电压，并在第二节点处将低输入逻辑电平电压拉高第二节点与所述第一逆变器装置串联的电路元件，用于将所述第一逆变器装置连接到电压源，所述电压源响应于低逻辑电平输入电压而以所述第二电压电平提供上拉信号; 以及响应于第二节点处的下拉电压的电路，用于停用第一电路元件，从而防止通过第一逆变器装置接地的漏电流。在第二节点处实现稳定的电压切换，以消除在第二电压电平提供上拉信号的电压源和接收器输入之间的泄漏电流。

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