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    • 4. 发明申请
    • ACCELERATOR CIRCUIT AND IMAGE PROCESSING APPARATUS
    • 加速电路和图像处理装置
    • US20150302283A1
    • 2015-10-22
    • US14681290
    • 2015-04-08
    • Hideki SUGIMOTOAkihiro MATSUOKAShimpei SONODA
    • Hideki SUGIMOTOAkihiro MATSUOKAShimpei SONODA
    • G06K15/02
    • H04N1/32561G06T1/20
    • An accelerator circuit for an image processing apparatus includes a buffer circuit that temporarily stores image data obtained from N (N>1) data sources and an arithmetic circuit that performs a predetermined arithmetic operation on pixel data. The buffer circuit includes N buffer memories and N 2D registers associated with the respective N data sources, a control circuit, and a selector. Each buffer memory temporarily stores image data obtained from a corresponding one of the N data sources. Each 2D register temporarily stores pixel data, which is a part of image data stored in a corresponding one of the N buffer memories, of an area of a predetermined size. The selector is controlled by the control circuit so as to select, when pixel data is stored in one of the N 2D registers, the pixel data and send the pixel data to the arithmetic circuit.
    • 一种用于图像处理装置的加速器电路包括缓冲电路,其临时存储从N(N> 1)个数据源获得的图像数据和对像素数据执行预定算术运算的运算电路。 缓冲电路包括与各个N个数据源相关联的N个缓冲存储器和N个2D寄存器,一个控制电路和一个选择器。 每个缓冲存储器临时存储从N个数据源中的相应一个获得的图像数据。 每个2D寄存器临时存储作为预定大小的区域中存储在相应的一个N个缓冲存储器中的图像数据的一部分的像素数据。 选择器由控制电路控制,以便当像素数据存储在N 2D寄存器之一中时,选择像素数据并将像素数据发送到运算电路。
    • 6. 发明申请
    • WORK INSTRUCTION SYSTEM AND IMAGE PROCESSING APPARATUS
    • 工作指导系统和图像处理设备
    • US20160358324A1
    • 2016-12-08
    • US15169001
    • 2016-05-31
    • Hideki SUGIMOTOAkihiro Matsuoka
    • Hideki SUGIMOTOAkihiro Matsuoka
    • G06T7/00G06K9/62G06K9/18H04N7/18
    • A system for outputting a work instruction, in which an image processing device that takes a picture of a photographic subject is connected to an output device is disclosed. The system includes an imaging unit that generates image data showing the picture of the photographic subject; an obtaining unit that obtains determination data used for determining whether a work process performed on the photographic subject is completed; an input unit that inputs reference material data indicating reference materials used for reference in the work process; a determination unit that determines whether the work process performed on the photographic subject is completed, the determination being made depending on whether the photographic subject in the image data is in a state indicated by the determination data; and an output unit that outputs, to the output device, reference material data for a work process specified in accordance with the determination.
    • 公开了一种用于输出工作指令的系统,其中将拍摄对象的照片的图像处理装置连接到输出装置。 该系统包括:成像单元,其生成表示拍摄对象的图像的图像数据; 获取单元,其获得用于确定对所述被摄体进行的作业处理是否完成的确定数据; 输入单元,其输入在工作过程中用于参考的参考材料的参考材料数据; 确定单元,其确定对所述拍摄对象执行的作业处理是否完成,所述确定是根据所述图像数据中的所述拍摄对象是否处于由所述确定数据指示的状态; 以及输出单元,其向所述输出装置输出用于根据所述确定指定的工作处理的参考材料数据。
    • 7. 发明授权
    • Accelerator circuit and image processing apparatus
    • 加速器电路和图像处理装置
    • US09363412B2
    • 2016-06-07
    • US14681290
    • 2015-04-08
    • Hideki SugimotoAkihiro MatsuokaShimpei Sonoda
    • Hideki SugimotoAkihiro MatsuokaShimpei Sonoda
    • G06F15/00G06F1/00G06K1/00G06K15/00H04N1/32G06T1/20
    • H04N1/32561G06T1/20
    • An accelerator circuit for an image processing apparatus includes a buffer circuit that temporarily stores image data obtained from N (N>1) data sources and an arithmetic circuit that performs a predetermined arithmetic operation on pixel data. The buffer circuit includes N buffer memories and N 2D registers associated with the respective N data sources, a control circuit, and a selector. Each buffer memory temporarily stores image data obtained from a corresponding one of the N data sources. Each 2D register temporarily stores pixel data, which is a part of image data stored in a corresponding one of the N buffer memories, of an area of a predetermined size. The selector is controlled by the control circuit so as to select, when pixel data is stored in one of the N 2D registers, the pixel data and send the pixel data to the arithmetic circuit.
    • 一种用于图像处理装置的加速器电路包括缓冲电路,其临时存储从N(N> 1)个数据源获得的图像数据和对像素数据执行预定算术运算的运算电路。 缓冲电路包括与各个N个数据源相关联的N个缓冲存储器和N个2D寄存器,一个控制电路和一个选择器。 每个缓冲存储器临时存储从N个数据源中的相应一个获得的图像数据。 每个2D寄存器临时存储作为预定大小的区域中存储在相应的一个N个缓冲存储器中的图像数据的一部分的像素数据。 选择器由控制电路控制,以便当像素数据存储在N 2D寄存器之一中时,选择像素数据并将像素数据发送到运算电路。