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    • 1. 发明申请
    • Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry
    • 使用系数对称的多相插值滤波器的最小面积集成电路实现
    • US20060120494A1
    • 2006-06-08
    • US11215319
    • 2005-08-29
    • Aditya BhuvanagiriHarvinder SinghRakesh MalikNitin Chawla
    • Aditya BhuvanagiriHarvinder SinghRakesh MalikNitin Chawla
    • H04B1/10
    • H03H17/0275H03H17/0657
    • A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.
    • 最小面积集成多相插值滤波器使用输入数据通道的系数对称性。 滤波器包括用于使输入信号与第一内部时钟信号同步的输入接口块; 用于提供多个延迟输出信号的存储块; 多路复用器输入接口块,用于响应于第二组内部控制信号输出用于产生镜像系数组的所选择的多个信号,用于产生镜像和/或对称系数集的系数块,以及输出多个滤波器 信号,用于对所述多个滤波信号执行选择,增益控制和数据宽度控制的输出多路复用器块,同步滤波后的信号的输出寄存器块以及用于实现滤波器并在两个通道之间延迟的控制块 以访问系数集合,从而最小化过滤器中的硬件。
    • 2. 发明申请
    • Device for implementing a sum of products expression
    • 用于实现产品表达式总和的设备
    • US20060153321A1
    • 2006-07-13
    • US11254935
    • 2005-10-20
    • Aditya BhuvanagiriRakesh MalikNitin Chawla
    • Aditya BhuvanagiriRakesh MalikNitin Chawla
    • H04B1/10
    • H03H17/0225
    • A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for generating the final output.
    • 用于实现产品总和表达式的装置包括接收用于产生第一组部分优化的表达项的系数组/复合和乘积表达式的第一组2-输入移位和加法(2SAD)块 通过在其中应用递归优化,第二组1输入Shift-and-Add(1SAD)块从2SAD块接收响应,用于通过在其中应用垂直优化来产生第二组部分优化的表达项,第二组2SAD块 接收来自第一组2SAD块和第二组1SAD块的递归和垂直优化的响应,用于通过在其中应用水平优化来产生第三组部分优化的表达项,第二组2SAD块从块接收响应以产生 通过应用分解和因式分解的第四组部分优化表达式,以及从第四组接收响应的第五组2SAD块 的2SAD块,用于生成最终输出。
    • 6. 发明申请
    • CONTROLLING VIDEO ENCODING USING AUDIO INFORMATION
    • 使用音频信息控制视频编码
    • US20110103468A1
    • 2011-05-05
    • US12612104
    • 2009-11-04
    • Chandra Mouli PolisettyAditya Bhuvanagiri
    • Chandra Mouli PolisettyAditya Bhuvanagiri
    • H04N7/12
    • H04N7/50G10L25/78H04N7/148H04N19/115H04N19/124H04N19/132H04N19/61H04N21/233H04N21/234363H04N21/234381H04N21/2402
    • A video encoder may reduce bandwidth consumption by skipping encoding of or reducing an encoding rate of video frames corresponding to silent audio frames, that is, audio frames that do not include speech data. In one example, an apparatus includes a video encoder comprising a coding unit configured to encode video data in a first or second mode and a mode select unit configured to receive an indication of whether encoded audio data corresponding to the video data to be encoded includes speech data. When the audio data includes speech data, the mode select unit selects the first mode, and when the audio data does not include speech data, the mode select unit selects the second mode. The second mode consumes relatively less bandwidth, e.g., by reducing a bitrate, modifying a quantization parameter to increase quantization, and/or reducing a frame rate relative to the first mode.
    • 视频编码器可以通过跳过对应于静音音频帧的视频帧的编码或减少编码率来减少带宽消耗,即不包括语音数据的音频帧。 在一个示例中,一种装置包括:视频编码器,包括被配置为以第一或第二模式编码视频数据的编码单元和被配置为接收与要编码的视频数据相对应的编码音频数据的指示包括语音 数据。 当音频数据包括语音数据时,模式选择单元选择第一模式,并且当音频数据不包括语音数据时,模式选择单元选择第二模式。 第二模式例如通过减少比特率,修改量化参数以增加量化和/或降低相对于第一模式的帧速率来消耗相对较小的带宽。
    • 7. 发明授权
    • Device for implementing a sum of products expression
    • 用于实现产品表达式总和的设备
    • US07917569B2
    • 2011-03-29
    • US11254935
    • 2005-10-20
    • Aditya BhuvanagiriRakesh MalikNitin Chawla
    • Aditya BhuvanagiriRakesh MalikNitin Chawla
    • G06F7/00
    • H03H17/0225
    • A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for generating the final output.
    • 用于实现产品总和表达式的装置包括接收用于产生第一组部分优化的表达项的系数组/复合和乘积表达式的第一组2-输入移位和加法(2SAD)块 通过在其中应用递归优化,第二组1输入Shift-and-Add(1SAD)块从2SAD块接收响应,用于通过在其中应用垂直优化来产生第二组部分优化的表达项,第二组2SAD块 接收来自第一组2SAD块和第二组1SAD块的递归和垂直优化的响应,用于通过在其中应用水平优化来产生第三组部分优化的表达项,第二组2SAD块从块接收响应以产生 通过应用分解和因式分解的第四组部分优化表达式,以及从第四组接收响应的第五组2SAD块 的2SAD块,用于生成最终输出。
    • 8. 发明授权
    • Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry
    • 使用系数对称的多相插值滤波器的最小面积集成电路实现
    • US07698355B2
    • 2010-04-13
    • US11215319
    • 2005-08-29
    • Aditya BhuvanagiriHarvinder SinghRakesh MalikNitin Chawla
    • Aditya BhuvanagiriHarvinder SinghRakesh MalikNitin Chawla
    • G06F17/17G06F15/00G11C19/00H04B1/10
    • H03H17/0275H03H17/0657
    • A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.
    • 最小面积集成多相插值滤波器使用输入数据通道的系数对称性。 滤波器包括用于使输入信号与第一内部时钟信号同步的输入接口块; 用于提供多个延迟输出信号的存储块; 多路复用器输入接口块,用于响应于第二组内部控制信号输出用于产生镜像系数组的所选择的多个信号,用于产生镜像和/或对称系数集的系数块,以及输出多个滤波器 信号,用于对所述多个滤波信号执行选择,增益控制和数据宽度控制的输出多路复用器块,同步滤波后的信号的输出寄存器块以及产生用于实现滤波器的时钟信号并在两个通道之间延迟的控制块 以访问系数集合,从而最小化过滤器中的硬件。