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1. 发明授权

US08659318B1 Systems and methods for implementing tristate signaling by using encapsulated unidirectional signals 有权
标题翻译：通过使用封装的单向信号实现三态信令的系统和方法
公开(公告)号：US08659318B1
公开(公告)日：2014-02-25
申请号：US12889735
申请日：2010-09-24
申请人： Brandon Lewis Gordon , Kent Orthner , Aaron Ferrucci , David Van Brink
发明人： Brandon Lewis Gordon , Kent Orthner , Aaron Ferrucci , David Van Brink
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03M5/18 , H03M5/16
摘要： Systems and methods for implementing tristate signaling are described. The systems include an integrated circuit that further includes a tristate system. The tristate system converts an encapsulated unidirectional signal into a tristate signal. A relation between multiple unidirectional signals and the tristate signal is established by encapsulating the unidirectional signals to represent the tristate signal. The establishment of the relation facilitates control of the tristate signal by controlling the encapsulated unidirectional signals.
摘要翻译：描述了实现三态信令的系统和方法。该系统包括还包括三态系统的集成电路。三态系统将封装的单向信号转换成三态信号。通过封装单向信号来表示三态信号，建立多个单向信号与三态信号之间的关系。该关系的建立便于通过控制封装的单向信号来控制三态信号。

2. 发明授权

US08578075B1 Performance constraints for system synthesis 有权
标题翻译：系统综合性能约束
公开(公告)号：US08578075B1
公开(公告)日：2013-11-05
申请号：US11674076
申请日：2007-02-12
申请人： Aaron Ferrucci , Silvio Brugada
发明人： Aaron Ferrucci , Silvio Brugada
IPC分类号： G06F13/12
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： Methods and apparatus are provided for receiving performance constraints for implementing a system. A system tool receives constraints such as throughput, latency, power consumption, resource usage, etc. and generates an interconnection fabric using the constraint information. The interconnection fabric includes ports adapters used to connect master components and slave components. In some instances, port adapters and components are intelligently selected and connected using the constraint information.
摘要翻译：提供了用于接收实现系统的性能约束的方法和装置。系统工具接收吞吐量，延迟，功耗，资源使用等约束，并使用约束信息生成互连结构。互连结构包括用于连接主组件和从组件的端口适配器。在某些情况下，使用约束信息智能地选择和连接端口适配器和组件。

3. 发明授权

US07822958B1 Booting mechanism for FPGA-based embedded system 有权
标题翻译：基于FPGA的嵌入式系统启动机制
公开(公告)号：US07822958B1
公开(公告)日：2010-10-26
申请号：US11372532
申请日：2006-03-10
申请人： Timothy P. Allen , Andrew Draper , Aaron Ferrucci , Kerry Veenstra
发明人： Timothy P. Allen , Andrew Draper , Aaron Ferrucci , Kerry Veenstra
IPC分类号： G06F9/00 , G06F9/24 , G06F13/00
CPC分类号： G06F9/4401
摘要： According to various embodiments of the present invention, a programmable device assembly includes an FPGA coupled to a nonvolatile serial configuration memory (e.g., serial flash memory) and a volatile fast bulk memory (e.g., SRAM or SDRAM). The nonvolatile serial configuration memory contains both the FPGA configuration data and CPU instructions. When a predetermined condition occurs, a serial memory access component that is hard coded on the FPGA automatically reads the configuration data from the nonvolatile serial configuration memory. The configuration data is used to configure the FPGA with various components, including a CPU, a boot ROM with code for a boot copier, and a bus structure. When the CPU boots, code for the boot copier is executed so that the CPU instructions are copied from the nonvolatile serial configuration memory to the volatile fast bulk memory. The CPU then executes the CPU instructions stored in the volatile fast bulk memory.
摘要翻译：根据本发明的各种实施例，可编程器件组件包括耦合到非易失性串行配置存储器（例如串行闪存）和易失性快速批量存储器（例如，SRAM或SDRAM）的FPGA。非易失性串行配置存储器包含FPGA配置数据和CPU指令。当发生预定条件时，在FPGA上硬编码的串行存储器访问部件自动从非易失性串行配置存储器读取配置数据。配置数据用于配置具有各种组件的FPGA，包括CPU，具有启动复印机代码的引导ROM和总线结构。当CPU引导时，执行引导复印机的代码，以便将CPU指令从非易失性串行配置存储器复制到易失性快速批量存储器。 CPU然后执行存储在易失性快速批量存储器中的CPU指令。

4. 发明授权

US07409608B1 Pseudo-random wait-state and pseudo-random latency components 有权
标题翻译：伪随机等待状态和伪随机延迟分量
公开(公告)号：US07409608B1
公开(公告)日：2008-08-05
申请号：US10829024
申请日：2004-04-20
申请人： Aaron Ferrucci , Todd Wayne
发明人： Aaron Ferrucci , Todd Wayne
IPC分类号： G01R31/28 , H04L1/18
CPC分类号： G06F13/4243 , G06F11/267
摘要： Methods and apparatus are provided for testing logic, particularly arbitration logic on a programmable chip. Secondary components on a programmable chip are configured with delay mechanisms operable to pseudo-randomly delay responses to requests received using arbitration logic. Requests are typically generated by primary components. The delay mechanisms can be used to test the ability of a programmable chip system to handle a variety of secondary component wait-state and latency characteristics. The delay mechanism can also be used to improve system performance.
摘要翻译：提供了用于测试逻辑的方法和装置，特别是可编程芯片上的仲裁逻辑。可编程芯片上的次要组件配置有延迟机制，可用于对使用仲裁逻辑接收到的请求进行伪随机延迟响应。请求通常由主要组件生成。延迟机制可用于测试可编程芯片系统处理各种次要组件等待状态和延迟特性的能力。延迟机制也可用于提高系统性能。

5. 发明授权

US07036107B1 Methods and apparatus for selective comment assertion 失效
公开(公告)号：US07036107B1
公开(公告)日：2006-04-25
申请号：US10461742
申请日：2003-06-12
申请人： Jeffrey Orion Pritchard , Tim Allen , Aaron Ferrucci , Chris Adler
发明人： Jeffrey Orion Pritchard , Tim Allen , Aaron Ferrucci , Chris Adler
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Methods and apparatus are provided for efficiently implementing a programmable chip using hardware description source files passed through multiple tools. A hardware description language source file is provided with mechanisms to allow tool-specific code to be handled by both a synthesis tool and by a simulation tool. Instructions are provided to direct a synthesis tool to read as code comments that a simulation tool is configured to disregard.

6. 发明授权

US08412918B1 Booting mechanism for FPGA-based embedded system 有权
标题翻译：基于FPGA的嵌入式系统启动机制
公开(公告)号：US08412918B1
公开(公告)日：2013-04-02
申请号：US12887982
申请日：2010-09-22
申请人： Timothy P. Allen , Andrew Draper , Aaron Ferrucci , Kerry Veenstra
发明人： Timothy P. Allen , Andrew Draper , Aaron Ferrucci , Kerry Veenstra
IPC分类号： G06F9/00 , G06F9/24 , G06F15/177 , G06F12/00
CPC分类号： G06F9/4401
摘要： According to various embodiments, a programmable device assembly includes an FPGA coupled to a nonvolatile serial configuration memory (e.g., serial flash memory) and a volatile fast bulk memory (e.g., SRAM or SDRAM). The nonvolatile serial configuration memory contains both the FPGA configuration data and CPU instructions. When a predetermined condition occurs, a serial memory access component that is hard coded on the FPGA automatically reads the configuration data from the nonvolatile serial configuration memory. The configuration data is used to configure the FPGA with various components, including a CPU, a boot ROM with code for a boot copier, and a bus structure. When the CPU boots, code for the boot copier is executed so that the CPU instructions are copied from the nonvolatile serial configuration memory to the volatile fast bulk memory. The CPU then executes the CPU instructions stored in the volatile fast bulk memory.
摘要翻译：根据各种实施例，可编程设备组件包括耦合到非易失性串行配置存储器（例如，串行闪存）和易失性快速批量存储器（例如，SRAM或SDRAM）的FPGA。非易失性串行配置存储器包含FPGA配置数据和CPU指令。当发生预定条件时，在FPGA上硬编码的串行存储器访问部件自动从非易失性串行配置存储器读取配置数据。配置数据用于配置具有各种组件的FPGA，包括CPU，具有启动复印机代码的引导ROM和总线结构。当CPU引导时，执行引导复印机的代码，以便将CPU指令从非易失性串行配置存储器复制到易失性快速批量存储器。 CPU然后执行存储在易失性快速批量存储器中的CPU指令。

7. 发明授权

US08015531B1 Deferred parameterization 有权
标题翻译：延期参数化
公开(公告)号：US08015531B1
公开(公告)日：2011-09-06
申请号：US12121549
申请日：2008-05-15
申请人： Aaron Ferrucci
发明人： Aaron Ferrucci
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/78 , G06F2217/84
摘要： Mechanisms are provided to allow programmable chip systems to support parameter ranges or a parameter space instead of fixed parameters. A system parameter such as signal width, frequency, clock rate, may be accessed and changed at run-time instead of requiring regeneration and reimplementation of the programmable chip system. Optimized parameter values can be determined and used to generate a programmable chip system having fixed parameter values.
摘要翻译：提供了用于允许可编程芯片系统支持参数范围或参数空间而不是固定参数的机制。可以在运行时访问和改变诸如信号宽度，频率，时钟速率的系统参数，而不需要可编程芯片系统的再生和重新实现。可以确定优化的参数值并用于生成具有固定参数值的可编程芯片系统。

8. 发明授权

US07395360B1 Programmable chip bus arbitration logic 有权
标题翻译：可编程芯片总线仲裁逻辑
公开(公告)号：US07395360B1
公开(公告)日：2008-07-01
申请号：US11232491
申请日：2005-09-21
申请人： Jeffrey Orion Pritchard , Kerry Veenstra , Aaron Ferrucci , Paul Metzgen
发明人： Jeffrey Orion Pritchard , Kerry Veenstra , Aaron Ferrucci , Paul Metzgen
IPC分类号： G06F13/364 , G06F13/14 , G06F13/26 , G06F13/38
CPC分类号： G06F13/364
摘要： Methods and apparatus are provided for implementing a bus arbitration priority encoding scheme with fairness. Bus arbitration logic is connected to multiple primary components or devices. The multiple primary components send requests to bus arbitration logic. The bus arbitration logic uses a request vector and an arbitration vector to determine a grant vector. The grant vector indicates what primary component should be allowed bus access.
摘要翻译：提供了用于实现公平的总线仲裁优先级编码方案的方法和装置。总线仲裁逻辑连接到多个主要组件或设备。多个主要组件向总线仲裁逻辑发送请求。总线仲裁逻辑使用请求向量和仲裁向量来确定授权向量。授权向量表示什么主要组件应该允许总线访问。

9. 发明授权

US07493584B1 Methods and apparatus for selective comment assertion 有权
标题翻译：选择性评论断言的方法和设备
公开(公告)号：US07493584B1
公开(公告)日：2009-02-17
申请号：US11354218
申请日：2006-02-13
申请人： Jeffrey Orion Pritchard , Tim Allen , Aaron Ferrucci , Chris Adler
发明人： Jeffrey Orion Pritchard , Tim Allen , Aaron Ferrucci , Chris Adler
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Methods and apparatus are provided for efficiently implementing a programmable chip using hardware description source files passed through multiple tools. A hardware description language source file is provided with mechanisms to allow tool-specific code to be handled by both a synthesis tool and by a simulation tool. Instructions are provided to direct a synthesis tool to read as code comments that a simulation tool is configured to disregard.
摘要翻译：提供了使用通过多个工具传递的硬件描述源文件来有效地实现可编程芯片的方法和装置。硬件描述语言源文件提供有允许特定于工具的代码由综合工具和仿真工具来处理的机制。提供说明以指导综合工具读取模拟工具被配置为忽略的代码注释。

10. 发明授权

US07472369B1 Embedding identification information on programmable devices 有权
标题翻译：在可编程设备上嵌入识别信息
公开(公告)号：US07472369B1
公开(公告)日：2008-12-30
申请号：US10861990
申请日：2004-06-03
申请人： Peter Bain , Kerry S. Veenstra , Timothy P. Allen , Aaron Ferrucci
发明人： Peter Bain , Kerry S. Veenstra , Timothy P. Allen , Aaron Ferrucci
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/66
摘要： Methods and apparatus are provided for embedding identification information on a programmable chip. Parameterizable components are selected for implementation on a programmable chip. Information relating to the parameterizable components is embedded on the programmable chip by storing the information using mechanisms such as look up tables associated with logic elements. Information can be used to identify types of components, versions of components, parameter sets, and other data associated with components implemented on the programmable device.
摘要翻译：提供了用于将识别信息嵌入到可编程芯片上的方法和装置。选择可参数化的组件以在可编程芯片上实现。通过使用诸如与逻辑元件相关联的查找表的机制来存储信息，将与可参数化组件相关的信息嵌入在可编程芯片上。信息可用于识别组件类型，组件版本，参数集以及与在可编程设备上实现的组件相关联的其他数据。

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