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1. 发明授权

US08622783B2 Method and system for controlling chemical mechanical polishing by controllably moving a slurry outlet 有权
标题翻译：通过可控地移动浆料出口来控制化学机械抛光的方法和系统
公开(公告)号：US08622783B2
公开(公告)日：2014-01-07
申请号：US13157447
申请日：2011-06-10
申请人： Axel Kiesel , Uwe Stoeckgen , John Lampett , Heiko Wundram
发明人： Axel Kiesel , Uwe Stoeckgen , John Lampett , Heiko Wundram
IPC分类号： B24B1/00 , B24B49/00 , B24B51/00
CPC分类号： B24B37/04 , B24B57/02
摘要： A system and a method of operating a chemical mechanical polishing (CMP) system comprises a slurry delivering unit configured for locally varying the supply of slurry while polishing the substrate. To this end, the slurry delivering unit may comprise at least one slurry outlet over a polishing pad of the CMP system, wherein the at least one slurry outlet is controllably movable to distribute slurry over the polishing pad.
摘要翻译：操作化学机械抛光（CMP）系统的系统和方法包括浆料输送单元，其被配置为在抛光衬底的同时局部地改变浆料的供应。为此，浆料输送单元可以包括在CMP系统的抛光垫上的至少一个浆料出口，其中至少一个浆料出口是可控制地移动的以将浆料分布在抛光垫上。

2. 发明授权

US08614123B2 Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures 有权
标题翻译：通过使用牺牲栅电极和牺牲自对准接触结构形成半导体器件的方法
公开(公告)号：US08614123B2
公开(公告)日：2013-12-24
申请号：US13305131
申请日：2011-11-28
申请人： Andy Wei , Peter Baars , Erik Geiss
发明人： Andy Wei , Peter Baars , Erik Geiss
IPC分类号： H01L21/8238
CPC分类号： H01L21/28079 , H01L21/76897 , H01L29/495 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure.
摘要翻译：本文公开了使用牺牲栅电极和牺牲自对准触点形成半导体器件的各种方法。在一个示例中，该方法包括形成由第一材料构成的两个间隔开的牺牲栅电极，形成包括第二材料的牺牲接触结构，其中第二材料相对于所述第一材料可选择性地蚀刻，并且执行蚀刻在两个间隔开的牺牲栅电极和牺牲接触结构之间进行选择性地相对于牺牲接触结构选择性地去除两个间隔开的牺牲栅极电极结构。

3. 发明授权

US08598007B1 Methods of performing highly tilted halo implantation processes on semiconductor devices 有权
标题翻译：在半导体器件上执行高度倾斜的晕圈注入工艺的方法
公开(公告)号：US08598007B1
公开(公告)日：2013-12-03
申请号：US13487351
申请日：2012-06-04
申请人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
发明人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/26586 , H01L21/823807 , H01L29/1083 , H01L29/66628 , H01L29/66636
摘要： One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate.
摘要翻译：本文公开的一种说明性方法包括分别形成包括用于第一晶体管器件和第二晶体管器件的帽层的第一和第二栅极结构，其中第一和第二晶体管彼此横向取向，执行第一晕圈离子注入工艺以形成第一晶体管的第一晕环注入区，其中盖层位于第一晶体管的第一栅极结构中的位置，从至少第二晶体管的第二栅极结构去除覆盖层，并且在去除覆盖层之后，执行第二晕圈离子注入工艺以形成用于第二晶体管的第二晕环注入区，其中第一和第二晕环注入工艺以相对于衬底的横向角度进行。

4. 发明授权

US08580672B2 Methods of forming bump structures that include a protection layer 有权
标题翻译：形成包括保护层的凸块结构的方法
公开(公告)号：US08580672B2
公开(公告)日：2013-11-12
申请号：US13280881
申请日：2011-10-25
申请人： Frank Kuechenmeister , Lothar Lehmann , Alexander Platz , Gotthard Jungnickel , Sven Kosgalwies
发明人： Frank Kuechenmeister , Lothar Lehmann , Alexander Platz , Gotthard Jungnickel , Sven Kosgalwies
IPC分类号： H01L21/44
CPC分类号： H01L23/49811 , H01L23/291 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/03009 , H01L2224/0345 , H01L2224/0401 , H01L2224/05022 , H01L2224/05166 , H01L2224/05558 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/1146 , H01L2224/1147 , H01L2224/11472 , H01L2224/11849 , H01L2224/13111 , H01L2924/00014 , H01L2924/01074 , H01L2924/01047 , H01L2924/01029 , H01L2224/05552
摘要： One illustrative method disclosed herein includes forming a conductive pad in a layer of insulating material, forming a passivation layer above the conductive pad, performing at least one etching process on the passivation layer to define an opening in the passivation layer that exposes at least a portion of the conductive pad, forming a protective layer on the passivation layer, in the opening and on the exposed portion of the conductive pad, forming a heat-curable material layer above the protective layer, performing an etching process to define a patterned heat-curable material layer having an opening that exposes a portion of the protective layer, performing an etching process on the protective layer to thereby expose at least a portion of the conductive pad and forming a conductive bump that is conductively coupled to the conductive pad.
摘要翻译：本文公开的一种说明性方法包括在绝缘材料层中形成导电焊盘，在导电焊盘上形成钝化层，在钝化层上执行至少一个蚀刻工艺，以限定钝化层中的至少一部分的导电焊盘，在导电焊盘的开口和暴露部分上在钝化层上形成保护层，在保护层上方形成可热固化的材料层，执行蚀刻工艺以限定图案化的可热固化材料层具有露出所述保护层的一部分的开口，对所述保护层进行蚀刻处理，从而暴露所述导电焊盘的至少一部分，并形成与所述导电焊盘导电耦合的导电凸块。

5. 发明授权

US08580643B2 Threshold voltage adjustment in a Fin transistor by corner implantation 有权
标题翻译：通过角落植入在Fin晶体管中的阈值电压调节
公开(公告)号：US08580643B2
公开(公告)日：2013-11-12
申请号：US13217009
申请日：2011-08-24
申请人： Tim Baldauf , Andy Wei , Tom Herrmann , Stefan Flachowsky , Ralf Illgen
发明人： Tim Baldauf , Andy Wei , Tom Herrmann , Stefan Flachowsky , Ralf Illgen
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886
摘要： When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.
摘要翻译：当在共同制造顺序中形成复杂的多个栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可以有意地“降低”多个栅极晶体管的阈值电压特性，从而获得多个栅极晶体管和平面晶体管的阈值电压特性。在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

6. 发明授权

US08575041B2 Repair of damaged surface areas of sensitive low-K dielectrics of microstructure devices after plasma processing by in situ treatment 有权
标题翻译：通过原位处理修复等离子体处理后微结构器件敏感的低K电介质损伤表面积
公开(公告)号：US08575041B2
公开(公告)日：2013-11-05
申请号：US13233590
申请日：2011-09-15
申请人： Matthias Schaller , Daniel Fischer , Thomas Oszinda
发明人： Matthias Schaller , Daniel Fischer , Thomas Oszinda
IPC分类号： H01L21/469
CPC分类号： H01L21/3105 , H01L21/02126 , H01L21/02203 , H01L21/31116 , H01L21/76814 , H01L21/76826
摘要： Damaged surface areas of low-k dielectric materials may be efficiently repaired by avoiding the saturation of dangling silicon bonds after a reactive plasma treatment on the basis of OH groups, as is typically applied in conventional process strategies. The saturation of the dangling bond may be accomplished by directly initiating a chemical reaction with appropriate organic species, thereby providing superior reaction conditions, which in turn results in a more efficient restoration of the dielectric characteristics.
摘要翻译：通过在常规工艺策略中通常应用的反应性等离子体处理后，通过避免在反应等离子体处理之后的悬挂硅键的饱和，可以有效地修复低k电介质材料的损坏的表面积。悬挂键的饱和可以通过直接引发与合适的有机物质的化学反应来实现，从而提供优异的反应条件，这又导致更有效的电介质特性的恢复。

7. 发明授权

US08564120B2 Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside 有权
标题翻译：半导体器件的温度关键器件区域的散热通过连接到衬底背面的热管进行散热
公开(公告)号：US08564120B2
公开(公告)日：2013-10-22
申请号：US12642989
申请日：2009-12-21
申请人： Anthony Mowry , David Farber , Fred Hause , Markus Lenski
发明人： Anthony Mowry , David Farber , Fred Hause , Markus Lenski
IPC分类号： H01L23/36 , H01L21/00
CPC分类号： H01L23/427 , H01L23/3677 , H01L23/481 , H01L23/522 , H01L27/16 , H01L2224/16 , H01L2224/73253 , H01L2924/01019 , H01L2924/13091 , H01L2924/15311 , H01L2924/3025 , H01L2924/00
摘要： By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.
摘要翻译：通过在半导体器件的温度关键区域中提供散热元件或热管，可以实现增强的性能，可靠性和封装密度。散热元件可以基于标准制造技术形成，并且可以定位成紧靠各个晶体管元件和/或可用于屏蔽特定的电路部分。

8. 发明授权

US08561446B2 Method and device for fabricating bonding wires on the basis of microelectronic manufacturing techniques 有权
标题翻译：在微电子制造技术的基础上制造接合线的方法和装置
公开(公告)号：US08561446B2
公开(公告)日：2013-10-22
申请号：US12562556
申请日：2009-09-18
申请人： Matthias Lehr , Frank Kuechenmeister , Frank Seliger
发明人： Matthias Lehr , Frank Kuechenmeister , Frank Seliger
IPC分类号： B21C3/02 , B21C1/00
CPC分类号： B21C3/02 , B21C3/04 , H01L24/43 , H01L24/45 , H01L24/745 , H01L2224/05624 , H01L2224/4321 , H01L2224/43847 , H01L2224/45012 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48624 , H01L2224/48724 , H01L2224/745 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01068 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/10253 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2224/48824 , H01L2924/00015
摘要： Bonding wires for sophisticated bonding applications may be efficiently formed on the basis of a corresponding template device that may be formed on the basis of semiconductor material, such as silicon, in combination with associated fabrication techniques, such as lithography and etch techniques. Hence, any appropriate diameter and cross-sectional shape may be obtained with a high degree of accuracy and reliability.
摘要翻译：可以基于可以基于诸如硅的半导体材料形成的相应的模板装置，结合相关的制造技术，例如光刻和蚀刻技术，有效地形成用于复杂粘合应用的粘合线。因此，可以以高精度和可靠性获得任何适当的直径和横截面形状。

9. 发明授权

US08557675B2 Methods of patterning features in a structure using multiple sidewall image transfer technique 有权
标题翻译：使用多侧壁图像转移技术在结构中构图特征的方法
公开(公告)号：US08557675B2
公开(公告)日：2013-10-15
申请号：US13305303
申请日：2011-11-28
申请人： Nicholas V. LiCausi
发明人： Nicholas V. LiCausi
IPC分类号： H01L29/06 , H01L21/033
CPC分类号： H01L21/0337 , H01L21/28132 , H01L21/3086 , H01L21/32139 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： Disclosed herein are methods of patterning features in a structure, such as a layer of material used in forming integrated circuit devices or in a semiconducting substrate, using a multiple sidewall image transfer technique. In one example, the method includes forming a first mandrel above a structure, forming a plurality of first spacers adjacent the first mandrel, forming a plurality of second mandrels adjacent one of the first spacers, and forming a plurality of second spacers adjacent one of the second mandrels. The method also includes performing at least one etching process to selectively remove the first mandrel and the second mandrels relative to the first spacers and the second spacers and thereby define an etch mask comprised of the first spacers and the second spacer and performing at least one etching process through the etch mask on the structure to define a plurality of features in the structure.
摘要翻译：本文公开了使用多侧壁图像转移技术在结构中形成特征的方法，例如用于形成集成电路器件或半导体衬底的材料层。在一个示例中，该方法包括在结构之上形成第一心轴，形成与第一心轴相邻的多个第一间隔件，邻近第一间隔件之一形成多个第二心轴，并且形成多个第二间隔件，第二个心轴该方法还包括执行至少一个蚀刻工艺，以相对于第一间隔件和第二间隔件选择性地移除第一心轴和第二心轴，从而限定由第一间隔件和第二间隔件组成的蚀刻掩模，并执行至少一个蚀刻通过结构上的蚀刻掩模处理以在结构中限定多个特征。

10. 发明授权

US08556083B2 Shale shakers with selective series/parallel flow path conversion 有权
标题翻译：具有选择性串联/并行流路转换的页岩振荡器
公开(公告)号：US08556083B2
公开(公告)日：2013-10-15
申请号：US12490492
申请日：2009-06-24
申请人： George Alexander Burnett
发明人： George Alexander Burnett
IPC分类号： B07B1/28
CPC分类号： E21B21/065 , B01D33/0376 , B01D33/41 , B07B1/28 , B07B1/46 , B07B13/16 , B07B13/18 , B07B2201/04 , B07B2230/01
摘要： Methods and systems are disclosed employing a shale shaker for processing a mixture of drilling fluid and solids with multiple screen assemblies and conversion apparatus for switching flow to the screen assemblies between series flow and parallel flow; and in one aspect, a screen or screens for screening lost circulation material.
摘要翻译：公开了使用用于处理具有多个筛网组件的钻井流体和固体的混合物的页岩振荡器的方法和系统，以及用于在串联流和平行流之间切换流向筛组件的转换装置; 并且在一个方面，用于筛选失去循环材料的筛网。

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