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1. 发明授权

US6163175A High voltage detector to control a power supply voltage pump for a 2.5 volt semiconductor process device 失效
标题翻译：高压检测器用于控制2.5伏半导体工艺装置的电源电压泵
公开(公告)号：US6163175A
公开(公告)日：2000-12-19
申请号：US276990
申请日：1999-03-26
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H02M3/07 , H03K5/24 , H03K5/153
CPC分类号： H03K5/2481 , H02M3/073
摘要： A high voltage detector circuit (FIG. 2) maintains a voltage (V.sub.2) on a reference line driven by a charge pump by turning the charge pump on with a signal (PUMPON) when the reference line voltage (V.sub.2) drops below a reference voltage (V.sub.1) plus a CMOS transistor threshold voltage. The high voltage detector is further configured to use transistors which have a maximum gate to drain, or gate to source voltage which exceeds the pin supply voltage to the chip. The high voltage detector includes comparators made up of a series of current mirrors driven by weak current sources enabling the circuit to use a minimum amount of power.
摘要翻译：高电压检测器电路（图2）通过在基准线电压（V2）下降到参考电压以下时，用信号（PUMPON）转动电荷泵来维持由电荷泵驱动的参考线上的电压（V2）（V1）加上CMOS晶体管阈值电压。高电压检测器还被配置为使用具有最大栅极漏极或栅极至源极电压的晶体管，栅极至源极电压超过芯片的引脚电源电压。高电压检测器包括由弱电流源驱动的一系列电流镜构成的比较器，使得电路能够使用最小量的功率。

2. 发明授权

US6133164A Fabrication of oxide regions having multiple thicknesses using minimized number of thermal cycles 有权
标题翻译：使用最小数量的热循环制造具有多个厚度的氧化物区域
公开(公告)号：US6133164A
公开(公告)日：2000-10-17
申请号：US256245
申请日：1999-02-23
申请人： Hyeon-Seag Kim
发明人： Hyeon-Seag Kim
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462
摘要： The present invention is a method for fabricating a plurality of oxide regions having a plurality of thicknesses on a semiconductor wafer. The present invention includes a step of depositing a first masking layer on the semiconductor wafer, and the first masking layer defines at least one first region for oxide growth of a first thickness. The present invention also includes a step of implanting oxygen ions into the at least one first region such that the first thickness of oxide on the at least one first region is relatively thicker. The first masking layer is then removed from the semiconductor wafer. The present invention further includes a step of depositing a second masking layer on the semiconductor wafer, and the second masking layer defines at least one second region for oxide growth of a second thickness. The present invention also includes a step of implanting nitrogen ions into the at least one second region such that the second thickness of oxide on the at least one second region is relatively thinner. The second masking layer is then removed from the semiconductor wafer. The present invention further includes the step of growing oxide on the at least one first region to have the first thickness and on the at least one second region to have the second thickness with a thermal process for the semiconductor wafer. During the thermal process, at least one third region of oxide may be grown to have a third thickness which is thinner than the oxide on the at least one first region and that is thicker than the oxide on the at least one second region since the at least one third region has not been exposed to oxygen ion implantation nor to nitrogen ion implantation.
摘要翻译：本发明是一种在半导体晶片上制造具有多个厚度的多个氧化物区域的方法。本发明包括在半导体晶片上沉积第一掩模层的步骤，并且第一掩蔽层限定用于第一厚度的氧化物生长的至少一个第一区域。本发明还包括将氧离子注入到至少一个第一区域中的步骤，使得至少一个第一区域上的第一厚度的氧化物相对较厚。然后从半导体晶片去除第一掩模层。本发明还包括在半导体晶片上沉积第二掩蔽层的步骤，并且第二掩蔽层限定用于第二厚度的氧化物生长的至少一个第二区域。本发明还包括将氮离子注入到至少一个第二区域中的步骤，使得至少一个第二区域上的第二厚度的氧化物相对较薄。然后从半导体晶片去除第二掩模层。本发明还包括在所述至少一个第一区域上生长氧化物以具有第一厚度并且在至少一个第二区域上具有用于半导体晶片的热处理的第二厚度的步骤。在热处理期间，可以生长至少一个第三区域的氧化物以具有比至少一个第一区域上的氧化物更薄的第三厚度，并且比第一区域上的氧化物厚，因为在至少一个第三区域没有暴露于氧离子注入和氮离子注入。

3. 发明授权

US6124730A Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources 失效
标题翻译：用于配置具有可变粒度组件的FPGA以提供对互连资源的时间共享访问的方法
公开(公告)号：US6124730A
公开(公告)日：2000-09-26
申请号：US212022
申请日：1998-12-15
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17748 , H03K19/1737 , H03K19/17736 , H03K19/17756 , H03K19/1778
摘要： A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.
摘要翻译：可变格式架构（VGA）用于从原始构建元素（CBE）合成每个给定任务的适当量的动态复用能力。这些可配置构建单元（CBE）中的未使用的组合被重新配置以执行进一步的逻辑功能来代替动态复用功能。每个CBE可以可编程地配置为提供不超过2对1的动态多路复用器（2：1 DyMUX）。然后可以将这种合成的2:1 DyMUX的动态可选输出输出到共享互连线上。 CBE的对可以合成，以有效地定义4：1的DyMUX，每个这样的4：1多路复用器占用可配置的构建块（CBB）结构。 CBB的对可以合成组合，以有效地定义8：1 DyMUX，每个这样合成的8：1多路复用器占据L形VGB结构（可变颗粒块）的垂直或水平延伸的腿部分。然后，VGB的如此配置的腿部分可以将由其8：1 DyMUX选择的信号输出到由VGB支路驱动的共享互连线上。 VGB的对或四重组可以合成组合，以有效地定义高阶N：1 DyMUX。

4. 发明授权

US6097664A Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan 有权
标题翻译：多端口SRAM单元阵列具有多个写入路径，包括用于通过可寻址端口进行写入和通过串行边界扫描
公开(公告)号：US6097664A
公开(公告)日：2000-08-01
申请号：US235356
申请日：1999-01-21
申请人： Bai Nguyen , Bradley A. Sharpe-Geisler , Herman M. Chang , Om P. Agrawal
发明人： Bai Nguyen , Bradley A. Sharpe-Geisler , Herman M. Chang , Om P. Agrawal
IPC分类号： G11C8/16 , G11C8/00
CPC分类号： G11C8/16
摘要： A serial scan chain extends into an array of SRAM cells within a multi-ported memory system for allowing serial introduction of write data into the SRAM cells and serial read-back of the data. Initial data may be pre-loaded into the SRAM cells by way of the serial scan chain before being read parallel-wise in response to read requests submitted through any of multiple, parallel data access ports of the system.
摘要翻译：串行扫描链扩展到多端口存储器系统中的SRAM单元阵列，用于将写入数据串行引入SRAM单元和数据的串行读回。响应于通过系统的多个并行数据访问端口中的任何一个提交的读取请求，初始数据可以通过串行扫描链预先加载到SRAM单元中，然后以并行方式读取。

5. 发明申请

US20010015449A1 Semiconductor - oxide - semiconductor capacitor formed in intergtated circuit 审中-公开
标题翻译：半导体 - 氧化物 - 半导体电容器形成在跨电路中
公开(公告)号：US20010015449A1
公开(公告)日：2001-08-23
申请号：US09782409
申请日：2001-02-12
申请人： Vantis Corporation
发明人： Bai Niguyen , Bradley A. Sharpe-Geisler
IPC分类号： H01L027/108
CPC分类号： H01L29/94 , H01L27/0629
摘要： An integrated capacitor structure includes first and second, conductive semiconductor portions spaced apart from one another where the first and second semiconductor portions are both of a same conductivity type (both N or both P). The integrated capacitor structure may be formed using same processes as are used for fabricating gate insulator and gate electrode parts of neighboring MOS transistors in a same integrated circuit.
摘要翻译：集成电容器结构包括彼此间隔开的第一和第二导电半导体部分，其中第一和第二半导体部分都具有相同的导电类型（N或两者均为P）。集成电容器结构可以使用与用于制造相同集成电路中的相邻MOS晶体管的栅极绝缘体和栅电极部分相同的工艺来形成。

6. 发明授权

US6130551A Synthesis-friendly FPGA architecture with variable length and variable timing interconnect 失效
标题翻译：具有可变长度和可变定时互连的合成友好的FPGA架构
公开(公告)号：US6130551A
公开(公告)日：2000-10-10
申请号：US8762
申请日：1998-01-19
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran , Bai Nguyen
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran , Bai Nguyen
IPC分类号： G06F17/50 , H03K19/177 , G06F7/38 , H03K19/173
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17736 , H03K19/17756 , H03K19/17796
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable Length Interconnect Architecture (VLI). Synthesis mapping exploits the diversified and symmetric resources of the VGA and VLI to efficiently pack function development into logic units of matched granularity and to transfer signals between logic units with interconnect lines of minimal length.
摘要翻译：具有多个行和列的逻辑功能单元的现场可编程门阵列器件（FPGA）以对称和互补的可变粒度架构（VGA）和可变长度互连架构（VLI）组织。综合映射利用VGA和VLI的多样化和对称资源，将功能开发有效地集成到匹配粒度的逻辑单元中，并在逻辑单元之间传输信号，并以最小长度的互连线传输信号。

7. 发明授权

US6102963A Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD's 失效
标题翻译：电可擦除和可重新编程的非易失性集成存储设备，具有系统内编程和验证（ISPAV）功能，可支持PLD的系统内重新配置
公开(公告)号：US6102963A
公开(公告)日：2000-08-15
申请号：US998978
申请日：1997-12-29
申请人： Om P. Agrawal
发明人： Om P. Agrawal
IPC分类号： H03K19/173 , H03K19/177 , G06F17/50 , G11C16/04
CPC分类号： H03K19/1736 , H03K19/17704
摘要： An in-system programmable and verifiable (ISPAV) configuration restoring device (CROP device) has an Electrically Erasable and reprogrammable, NonVolatile Integrated Storage array (e.g., a FLASH EE.sub.-- NVIS array) into which configuration instructions may be written for later readout during configuration restoration of a Programmable Logic Device (PLD) where the PLD has a volatile configuration memory. The volatile PLD may be an FPGA or a CPLD. The ISPAV CROP device includes a shared shift register through which configuration instructions read from the EE.sub.-- NVIS array are serially shifted out to a to-be-configured PLD. The shared shift register is also used for loading new configuration instructions into the EE.sub.-- NVIS array by way of a 4-wire interface such as JTAG and also for verifying proper writing of these instructions into the EE.sub.-- NVIS array.
摘要翻译：系统可编程和可验证（ISPAV）配置恢复设备（CROP设备）具有电可擦除和可重新编程的非易失性集成存储阵列（例如，FLASH EE-NVIS阵列），配置指令可在其中写入，以供配置期间稍后读取恢复可编程逻辑器件（PLD），其中PLD具有易失性配置存储器。易失性PLD可能是FPGA或CPLD。 ISPAV CROP设备包括共享移位寄存器，通过该共享移位寄存器将从EE-NVIS阵列读取的配置指令串行移出到待配置的PLD。共享移位寄存器还用于通过诸如JTAG的4线接口将新配置指令加载到EE-NVIS阵列中，并且还用于验证这些指令是否正确写入EE-NVIS阵列。

8. 发明授权

US6064595A Floating gate memory apparatus and method for selected programming thereof 有权
标题翻译：浮栅存储装置及其选择编程方法
公开(公告)号：US6064595A
公开(公告)日：2000-05-16
申请号：US220201
申请日：1998-12-23
申请人： Stewart G. Logie , Sunil D. Mehta , Steven J. Fong
发明人： Stewart G. Logie , Sunil D. Mehta , Steven J. Fong
IPC分类号： H01L21/8247 , G11C16/04 , G11C16/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/0441 , G11C16/10 , H01L29/7886
摘要： A method of creating a reverse breakdown condition in an array of memory cells arranged in columns and rows in the array, and an array structure are provided. The method comprises the steps of applying a first voltage on a first column connection coupling a first column of said cells, and a second voltage on a second column connection coupling a second column of said cells; and applying a third voltage on a first row connection coupling a first row of said cells, and applying said second voltage on a second row connection coupling a second row of said cells. In this aspect, the difference between the first voltage and the third voltage creates said reverse breakdown condition in at least one cell occupying said first column and first row. In a further aspect, each cell includes a floating gate and the method of the invention includes the step of programming one of said cells by coupling a control voltage to each floating gate. The structure includes a substrate having formed therein at least an Nth or Mth row-wise oriented well, each well isolated from adjacent ones of said wells. Also provided are at least an Nth and Mth word bit line formed by an Nth and Mth impurity regions in said substrate and at least an Nth and Mth array control gate lines. A plurality of memory cells, each cell formed in at least said Nth or Mth row-wise well, is further provided. Each cell comprises a drain, a floating gate, a drain connection one of said Nth or Mth word bit line (WBL), and a substrate well connection to one of said Nth or Mth wells, and a control gate connection to one of said Nth or Mth array control gate lines(ACG).
摘要翻译：提供了在阵列中以行和列排列的存储单元阵列中产生反向故障条件的方法，以及阵列结构。该方法包括以下步骤：在耦合所述单元的第一列的第一列连接上施加第一电压，以及在耦合所述单元的第二列的第二列连接上施加第二电压; 以及在耦合所述单元的第一行的第一行连接上施加第三电压，以及将耦合所述单元的第二行的第二行连接上施加所述第二电压。在这方面，第一电压和第三电压之间的差异在占据所述第一列和第一行的至少一个单元中产生所述反向击穿条件。在另一方面，每个单元包括浮动栅极，并且本发明的方法包括通过将控制电压耦合到每个浮动栅极来编程所述单元之一的步骤。该结构包括在其中形成有至少第N或第M行行取向阱的衬底，每个阱与相邻的所述阱分离。还提供了由所述衬底中的第N和第M杂质区形成的至少第N和第M字位线以及至少第N和第M阵列控制栅极线。还提供多个存储单元，每个单元形成在至少所述第N或第M行列井中。每个单元包括所述第N或第M字位线（WBL）之一的漏极，浮置栅极，漏极连接以及与所述第N或第M阱之一的衬底阱连接，以及到所述第N个或第M阵列控制栅极线（ACG）。

9. 发明授权

US6043969A Ballast resistors with parallel stacked NMOS transistors used to prevent secondary breakdown during ESD with 2.5 volt process transistors 失效
标题翻译：具有并联堆叠NMOS晶体管的镇流电阻器，用于防止ESD中的二次击穿，具有2.5伏过程晶体管
公开(公告)号：US6043969A
公开(公告)日：2000-03-28
申请号：US114718
申请日：1998-07-13
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0251
摘要： Electrostatic discharge (ESD) protection is provided for NMOS pull up transistors 700A-H and 702A-H of a 5.0 volt compatible output buffer using 2.5 volt process transistors. The ESD protection includes ballast resistors 701A-H and 703A-H separating individual pairs of NMOS pull up transistors 700A-H and 702A-H from the pad and from a power supply connection NV3. The ballast resistors enable turn on of additional pairs of NMOS pull up transistors after a first pair, such as 700A,702A turns on during an ESD event to prevent secondary breakdown in the first NMOS pair. Pairs of NMOS pull up transistors are used to prevent voltages across individual NMOS transistors from exceeding a 2.7 volt maximum while still enabling the transistors to provide 5.0 volts to the pad.
摘要翻译：使用2.5伏过程晶体管为5.0V兼容输出缓冲器的NMOS上拉晶体管700A-H和702A-H提供静电放电（ESD）保护。 ESD保护包括从焊盘和电源连接NV3分离各对NMOS上拉晶体管700A-H和702A-H的镇流电阻器701A-H和703A-H。镇流电阻器使得在ESD事件之后的第一对（例如700A，702A）导通之后，能够在另一对NMOS上拉晶体管上导通，以防止第一NMOS对中的次级击穿。一对NMOS上拉晶体管用于防止单个NMOS晶体管上的电压超过2.7伏最大值，同时仍然使晶体管能够向焊盘提供5.0伏特。

10. 发明授权

US06031365A Band gap reference using a low voltage power supply 失效
标题翻译：带隙参考使用低压电源
公开(公告)号：US06031365A
公开(公告)日：2000-02-29
申请号：US276991
申请日：1999-03-26
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： G05F3/30 , G05F3/16
CPC分类号： G05F3/30
摘要： A band gap reference includes an operational amplifier with an output (n23) driving the gate of three current source transistors (501-503). The first current source (501) drives the (+) opamp input (n20) and a transistor (511) functioning as a diode. The second current source (502) drives the (-) opamp input and a series resistor (R.sub.1) and a transistor (512) functioning as a diode. The third current source (503) drives a series resistor (R.sub.2) and diode connected transistor (513). The opamp includes first series transistors (521) and (524) connected between V.sub.DD and V.sub.SS, and second series transistors (522) and (525) connected between V.sub.DD and V.sub.SS. With only two series transistors between V.sub.DD and V.sub.SS at any point, only two times a CMOS transistor threshold drop (less than 1.8 volts) will occur enabling V.sub.DD to range from 1.8-3.6 volts without altering the band gap reference output voltage (V.sub.DIODE). Further, CMOS transistors in the circuit may operate with a 2.7 volt maximum gate to source, or gate to drain voltage.
摘要翻译：带隙基准包括具有驱动三个电流源晶体管（501-503）的栅极的输出（n23）的运算放大器。第一电流源（501）驱动（+）运算放大器输入（n20）和用作二极管的晶体管（511）。第二电流源（502）驱动（ - ）运算放大器输入和用作二极管的串联电阻（R1）和晶体管（512）。第三电流源（503）驱动串联电阻器（R2）和二极管连接晶体管（513）。运算放大器包括连接在VDD和VSS之间的第一串联晶体管（521）和（524）以及连接在VDD和VSS之间的第二串联晶体管（522）和（525）。只要VDD和VSS之间只有两个串联晶体管，任何时候只会产生CMOS晶体管阈值下降（小于1.8伏特）的两倍，使得VDD可以在1.8-3.6伏范围内，而不会改变带隙基准输出电压（VDIODE）。此外，电路中的CMOS晶体管可以以2.7伏的最大栅极至源极或栅极至漏极电压工作。

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