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1. 发明授权

US6163175A High voltage detector to control a power supply voltage pump for a 2.5 volt semiconductor process device 失效
标题翻译：高压检测器用于控制2.5伏半导体工艺装置的电源电压泵
公开(公告)号：US6163175A
公开(公告)日：2000-12-19
申请号：US276990
申请日：1999-03-26
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H02M3/07 , H03K5/24 , H03K5/153
CPC分类号： H03K5/2481 , H02M3/073
摘要： A high voltage detector circuit (FIG. 2) maintains a voltage (V.sub.2) on a reference line driven by a charge pump by turning the charge pump on with a signal (PUMPON) when the reference line voltage (V.sub.2) drops below a reference voltage (V.sub.1) plus a CMOS transistor threshold voltage. The high voltage detector is further configured to use transistors which have a maximum gate to drain, or gate to source voltage which exceeds the pin supply voltage to the chip. The high voltage detector includes comparators made up of a series of current mirrors driven by weak current sources enabling the circuit to use a minimum amount of power.
摘要翻译：高电压检测器电路（图2）通过在基准线电压（V2）下降到参考电压以下时，用信号（PUMPON）转动电荷泵来维持由电荷泵驱动的参考线上的电压（V2）（V1）加上CMOS晶体管阈值电压。高电压检测器还被配置为使用具有最大栅极漏极或栅极至源极电压的晶体管，栅极至源极电压超过芯片的引脚电源电压。高电压检测器包括由弱电流源驱动的一系列电流镜构成的比较器，使得电路能够使用最小量的功率。

2. 发明授权

US6133164A Fabrication of oxide regions having multiple thicknesses using minimized number of thermal cycles 有权
标题翻译：使用最小数量的热循环制造具有多个厚度的氧化物区域
公开(公告)号：US6133164A
公开(公告)日：2000-10-17
申请号：US256245
申请日：1999-02-23
申请人： Hyeon-Seag Kim
发明人： Hyeon-Seag Kim
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462
摘要： The present invention is a method for fabricating a plurality of oxide regions having a plurality of thicknesses on a semiconductor wafer. The present invention includes a step of depositing a first masking layer on the semiconductor wafer, and the first masking layer defines at least one first region for oxide growth of a first thickness. The present invention also includes a step of implanting oxygen ions into the at least one first region such that the first thickness of oxide on the at least one first region is relatively thicker. The first masking layer is then removed from the semiconductor wafer. The present invention further includes a step of depositing a second masking layer on the semiconductor wafer, and the second masking layer defines at least one second region for oxide growth of a second thickness. The present invention also includes a step of implanting nitrogen ions into the at least one second region such that the second thickness of oxide on the at least one second region is relatively thinner. The second masking layer is then removed from the semiconductor wafer. The present invention further includes the step of growing oxide on the at least one first region to have the first thickness and on the at least one second region to have the second thickness with a thermal process for the semiconductor wafer. During the thermal process, at least one third region of oxide may be grown to have a third thickness which is thinner than the oxide on the at least one first region and that is thicker than the oxide on the at least one second region since the at least one third region has not been exposed to oxygen ion implantation nor to nitrogen ion implantation.
摘要翻译：本发明是一种在半导体晶片上制造具有多个厚度的多个氧化物区域的方法。本发明包括在半导体晶片上沉积第一掩模层的步骤，并且第一掩蔽层限定用于第一厚度的氧化物生长的至少一个第一区域。本发明还包括将氧离子注入到至少一个第一区域中的步骤，使得至少一个第一区域上的第一厚度的氧化物相对较厚。然后从半导体晶片去除第一掩模层。本发明还包括在半导体晶片上沉积第二掩蔽层的步骤，并且第二掩蔽层限定用于第二厚度的氧化物生长的至少一个第二区域。本发明还包括将氮离子注入到至少一个第二区域中的步骤，使得至少一个第二区域上的第二厚度的氧化物相对较薄。然后从半导体晶片去除第二掩模层。本发明还包括在所述至少一个第一区域上生长氧化物以具有第一厚度并且在至少一个第二区域上具有用于半导体晶片的热处理的第二厚度的步骤。在热处理期间，可以生长至少一个第三区域的氧化物以具有比至少一个第一区域上的氧化物更薄的第三厚度，并且比第一区域上的氧化物厚，因为在至少一个第三区域没有暴露于氧离子注入和氮离子注入。

3. 发明授权

US6124730A Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources 失效
标题翻译：用于配置具有可变粒度组件的FPGA以提供对互连资源的时间共享访问的方法
公开(公告)号：US6124730A
公开(公告)日：2000-09-26
申请号：US212022
申请日：1998-12-15
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17748 , H03K19/1737 , H03K19/17736 , H03K19/17756 , H03K19/1778
摘要： A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.
摘要翻译：可变格式架构（VGA）用于从原始构建元素（CBE）合成每个给定任务的适当量的动态复用能力。这些可配置构建单元（CBE）中的未使用的组合被重新配置以执行进一步的逻辑功能来代替动态复用功能。每个CBE可以可编程地配置为提供不超过2对1的动态多路复用器（2：1 DyMUX）。然后可以将这种合成的2:1 DyMUX的动态可选输出输出到共享互连线上。 CBE的对可以合成，以有效地定义4：1的DyMUX，每个这样的4：1多路复用器占用可配置的构建块（CBB）结构。 CBB的对可以合成组合，以有效地定义8：1 DyMUX，每个这样合成的8：1多路复用器占据L形VGB结构（可变颗粒块）的垂直或水平延伸的腿部分。然后，VGB的如此配置的腿部分可以将由其8：1 DyMUX选择的信号输出到由VGB支路驱动的共享互连线上。 VGB的对或四重组可以合成组合，以有效地定义高阶N：1 DyMUX。

4. 发明授权

US6097664A Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan 有权
标题翻译：多端口SRAM单元阵列具有多个写入路径，包括用于通过可寻址端口进行写入和通过串行边界扫描
公开(公告)号：US6097664A
公开(公告)日：2000-08-01
申请号：US235356
申请日：1999-01-21
申请人： Bai Nguyen , Bradley A. Sharpe-Geisler , Herman M. Chang , Om P. Agrawal
发明人： Bai Nguyen , Bradley A. Sharpe-Geisler , Herman M. Chang , Om P. Agrawal
IPC分类号： G11C8/16 , G11C8/00
CPC分类号： G11C8/16
摘要： A serial scan chain extends into an array of SRAM cells within a multi-ported memory system for allowing serial introduction of write data into the SRAM cells and serial read-back of the data. Initial data may be pre-loaded into the SRAM cells by way of the serial scan chain before being read parallel-wise in response to read requests submitted through any of multiple, parallel data access ports of the system.
摘要翻译：串行扫描链扩展到多端口存储器系统中的SRAM单元阵列，用于将写入数据串行引入SRAM单元和数据的串行读回。响应于通过系统的多个并行数据访问端口中的任何一个提交的读取请求，初始数据可以通过串行扫描链预先加载到SRAM单元中，然后以并行方式读取。

5. 发明授权

US6128770A Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block) 失效
标题翻译：可配置逻辑阵列，包括IOB以延长线互连装置，用于从每个IOB（输入/输出块）提供对多个延长线的可选择访问，
公开(公告)号：US6128770A
公开(公告)日：2000-10-03
申请号：US37095
申请日：1998-03-09
申请人： Om Prakash Agrawal , Michael James Wright , Ju Shen
发明人： Om Prakash Agrawal , Michael James Wright , Ju Shen
IPC分类号： G06F7/00 , G06F7/575 , G06F17/50 , H03K17/693 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17744
摘要： A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. A selector is provided with each of peripherally distributed IOB's of each row or column for selecting an output signal from plural one of long lines that extend perpendicularly relative to the peripheral boundary at which the IOB resides.
摘要翻译：可编程集成电路包括可配置逻辑块（CLB），可配置输入/输出块（IOB）和可配置互连网络，用于在CLB和IOB之间提供程序定义的信号路由。每个行或列的每个外围分布的IOB的选择器被提供，用于从IOB所在的外围边界垂直延伸的多条长行中选择输出信号。

6. 发明授权

US6127843A Dual port SRAM memory for run time use in FPGA integrated circuits 失效
标题翻译：双端口SRAM存储器用于运行时间用于FPGA集成电路
公开(公告)号：US6127843A
公开(公告)日：2000-10-03
申请号：US996049
申请日：1997-12-22
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes plural columns of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each logic function unit (VGB) is organized to process a nibble of data. Each embedded memory block is multi-ported and organized to store addressable nibbles of data. Interconnect resources are provided for efficiently transferring nibbles of data between the logic function units (VGB's) and corresponding memory blocks. Further interconnect resources (SVIC's) are provided for supplying address and control signals to each memory block. In one embodiment each memory block has at least one read-only port and at least one read/write port that are individually addressable and individually switchable into high output impedance tri-state modes.
摘要翻译：具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多列嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。每个逻辑功能单元（VGB）被组织以处理数据的半字节。每个嵌入式存储器块都是多端口的并被组织以存储可寻址的数据的半字节。提供互连资源，用于在逻辑功能单元（VGB）和相应的存储块之间有效传输数据的半字节。提供了进一步的互连资源（SVIC），用于向每个存储块提供地址和控制信号。在一个实施例中，每个存储器块具有至少一个只读端口和至少一个读/写端口，其可单独寻址并且可单独切换到高输出阻抗三态模式。

7. 发明授权

US06093946A EEPROM cell with field-edgeless tunnel window using shallow trench isolation process 失效
标题翻译：具有无源隧道窗的EEPROM单元采用浅沟槽隔离工艺
公开(公告)号：US06093946A
公开(公告)日：2000-07-25
申请号：US26814
申请日：1998-02-20
申请人： Xiao-Yu Li , Sunil D. Mehta
发明人： Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/7883
摘要： An improved EEPROM cell having a field-edgeless tunnel window is provided which is fabricated by a STI process so as to produce reliable endurance and data retention. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The tunneling oxide layer defines a tunnel window which allows for programming and erasing of the floating gate by tunneling electrons therethrough. The programmable junction region has a width dimension and a length dimension so as to define a first area. The tunnel window has a width dimension and a length dimension so as to define a second area. The second area of the tunnel window is completely confined within the first area of the programmable junction region so as to form a field-edgeless tunnel window.
摘要翻译：提供了具有场无边界隧道窗的改进的EEPROM单元，其通过STI工艺制造，以便产生可靠的耐久性和数据保持。 EEPROM单元包括浮置栅极，可编程结区域和分离可编程结区域和浮置栅极的隧穿氧化物层。隧道氧化物层限定隧道窗口，其允许通过隧穿电子进行浮动栅极的编程和擦除。可编程连接区域具有宽度尺寸和长度尺寸，以便限定第一区域。隧道窗口具有宽度尺寸和长度尺寸，以便限定第二区域。隧道窗口的第二区域被完全限制在可编程连接区域的第一区域内，从而形成无边界的隧道窗口。

8. 发明授权

US6034893A Non-volatile memory cell having dual avalanche injection elements 有权
标题翻译：具有双雪崩注入元件的非易失性存储单元
公开(公告)号：US6034893A
公开(公告)日：2000-03-07
申请号：US334052
申请日：1999-06-15
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： G11C16/04 , H01L21/8247 , H01L29/861
CPC分类号： H01L29/8616 , G11C16/0441 , H01L27/11521 , H01L27/11558
摘要： A non-volatile memory cell includes a well region formed in a semiconductor substrate. First and second avalanche injection elements reside in the well region. A bifurcated floating-gate electrode includes a first segment overlying the first avalanche injection element and a second segment overlying the second avalanche injection element. A first contact region resides in the well region adjacent to the first segment of the floating-gate electrode, and a second contact region resides in the well region adjacent to the second segment of the floating-gate electrode. Upon the application of programming or erasing voltage, electrical charge is independently transferred to each of the first and second segments of the floating-gate electrode from the first and second avalanche injection elements, respectively.
摘要翻译：非易失性存储单元包括形成在半导体衬底中的阱区。第一和第二雪崩注入元件驻留在井区域中。分叉浮栅电极包括覆盖第一雪崩注入元件的第一段和覆盖第二雪崩注入元件的第二段。第一接触区域位于与浮栅电极的第一段相邻的阱区中，并且第二接触区位于与浮栅电极的第二段相邻的阱区中。在施加编程或擦除电压时，电荷分别独立地从第一和第二雪崩注入元件转移到浮栅电极的第一和第二段中的每一个。

9. 发明授权

US5990702A Flexible direct connections between input/output blocks (IOBs) and variable grain blocks (VGBs) in FPGA integrated circuits 失效
标题翻译： FPGA集成电路中的输入/输出块（IOB）和可变晶粒块（VGB）之间的灵活的直接连接
公开(公告)号：US5990702A
公开(公告)日：1999-11-23
申请号：US995612
申请日：1997-12-22
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Giap H. Tran
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs). An inter-connect network provides routing of signals between the IOBs and VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-producing resources. The IOBs are arranged along a top, left, bottom and right side of the plurality of VGBs. An IOB includes a 1) delay for timing input signals, 2) a configurable output latch which may be set or reset responsive to control signals, and 3) transistor for controlling a NOR line. The IOB is programmably configured to the inter-connect network which includes vertical and horizontal inter-connect channels comprising adjacent inter-connect lines. The IOB inputs are connected to adjacent inter-connect lines including 1) direct connect input lines from adjacent super-VGBs, 2) MaxL lines, and 3) dendrite lines from adjacent dendrites. The IOB outputs are connected to 1) MaxL lines, 2) dendrite lines in adjacent dendrites, 3) NOR lines, and 4) direct connect output lines to adjacent super-VGBs. Dendrites for routing signals along the periphery of the plurality of VGBs are positioned between the IOBs and super-VGBs. Dendrites include a plurality of I/O switchboxes and dendrite lines. The I/O switchboxes are coupled to vertical and horizontal inter-connect channels. The inter-connect network includes a direct connect architecture between IOBs and adjacent super-VGBs. Dedicated connections between corner and non-corner IOBs provide direct connect inputs and outputs to and from CBBs in a super-VGB.
摘要翻译：现场可编程门阵列（FPGA）装置包括多个输入/输出块（IOB）和可变粒子块（VGB）。互连网络提供IOB和VGB之间的信号路由。 VGB包括具有功能生成资源的多个L组织CBB（可配置逻辑块）。 IOB沿着多个VGB的顶部，左侧，底部和右侧布置。 IOB包括1）用于定时输入信号的延迟，2）响应于控制信号可以被设置或复位的可配置输出锁存器，以及3）用于控制NOR线路的晶体管。 IOB可编程地配置到包括相邻连接线之间的垂直和水平互连通道的互连网络。 IOB输入连接到相邻的互连线，包括1）直接连接相邻超VGB的输入线，2）MaxL线，以及3）相邻枝晶的枝晶线。 IOB输出连接到1）MaxL线，2）相邻枝晶中的枝晶线，3）NOR线，以及4）将输出线直接连接到相邻的超VGB。沿着多个VGB的周边路由信号的树枝状晶体位于IOB和超级VGB之间。树枝包括多个I / O开关盒和枝晶线。 I / O开关盒耦合到垂直和水平互连通道。互连网络包括IOB和相邻超级VGB之间的直接连接体系结构。转角和非拐角IOB之间的专用连接可在超级VGB中向CBB提供直接连接输入和输出。

10. 发明授权

US5969992A EEPROM cell using P-well for tunneling across a channel 失效
标题翻译：使用P阱的EEPROM单元进行跨通道的隧穿
公开(公告)号：US5969992A
公开(公告)日：1999-10-19
申请号：US217647
申请日：1998-12-21
申请人： Sunil D. Mehta , Xiao-Yu Li
发明人： Sunil D. Mehta , Xiao-Yu Li
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11558
摘要： An EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a P-well of a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.
摘要翻译：描述了通过遍及分离的晶体管通道的整个部分的电子隧道编程和擦除的EEPROM单元。 EEPROM单元具有形成在半导体衬底的P阱中的三个晶体管。三个晶体管是隧道晶体管（NMOS），感测晶体管（NMOS）和读取晶体管（NMOS）。发生电子隧穿，以在浮动栅极和感测通道之间发生足够的电压电势时通过感测隧道氧化物层来编程EEPROM单元。当浮置栅极和隧穿通道之间产生足够的电压电势时，也会发生电子隧穿，以通过隧道氧化物层擦除EEPROM单元。

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