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1. 发明授权

US5861333A Method of tunnel window process for EEPROM cell technology 失效
标题翻译： EEPROM单元技术的隧道窗口处理方法
公开(公告)号：US5861333A
公开(公告)日：1999-01-19
申请号：US738328
申请日：1996-10-25
申请人： Kun-Chi Lin
发明人： Kun-Chi Lin
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： The present invention includes forming a first field oxide region (FOX) on a substrate. Buried N.sup.+ regions are then formed. Subsequently, a plurality of second FOX regions are formed. A tunneling window region between the second FOX regions is narrowed by the formation of the second FOX regions. Then a tunnel oxide is formed on the substrate. A first polysilicon layer is deposited on the first FOX, the second FOXs, the gate oxide, the tunnel oxide and the substrate. An etching step is used to define the floating gate. A dielectric layer is formed on the floating gate. A second polysilicon layer is then formed on the dielectric layer. The second polysilicon layer and the dielectric layer are etched. An ion implantation step is used to form source and drain of the gate.
摘要翻译：本发明包括在基板上形成第一场氧化物区域（FOX）。然后形成掩埋的N +区。随后，形成多个第二FOX区域。第二FOX区域之间的隧道窗口区域由于形成第二FOX区域而变窄。然后在衬底上形成隧道氧化物。第一多晶硅层沉积在第一FOX，第二FOX，栅极氧化物，隧道氧化物和衬底上。蚀刻步骤用于限定浮动栅极。在浮栅上形成介电层。然后在电介质层上形成第二多晶硅层。蚀刻第二多晶硅层和电介质层。离子注入步骤用于形成栅极的源极和漏极。

2. 发明授权

US09847331B2 Semiconductor integrated circuit 有权
公开(公告)号：US09847331B2
公开(公告)日：2017-12-19
申请号：US15358143
申请日：2016-11-22
申请人： UNITED MICROELECTRONICS CORP.
发明人： Po-Chao Tsao
IPC分类号： H01L27/06 , H01L27/088 , H01L21/8234 , H01L29/06 , H01L29/78 , H01L49/02 , H01L29/40
CPC分类号： H01L27/0886 , H01L21/823431 , H01L27/0611 , H01L27/0629 , H01L28/20 , H01L29/0649 , H01L29/0653 , H01L29/408 , H01L29/7816 , H01L29/7817 , H01L29/7835 , H01L29/7851
摘要： A semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an LDMOS device positioned on the substrate. The substrate includes a plurality of first isolation structures and a plurality of second isolation structures. A depth of the first isolation structures is smaller than a depth of the second isolation structures. The multi-gate transistor device includes a plurality of first fin structures and a first gate electrode. The first fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The first gate electrode is intersectionally arranged with the first fin structures, and covers a portion of each first fin structure. The LDMOS device includes a second gate electrode covering on the substrate. The LDMOS device is electrically isolated from the multi-gate transistor device by another second isolation structure.

3. 发明授权

US07344954B2 Method of manufacturing a capacitor deep trench and of etching a deep trench opening 有权
标题翻译：制造电容器深沟槽并蚀刻深沟槽开口的方法
公开(公告)号：US07344954B2
公开(公告)日：2008-03-18
申请号：US11306560
申请日：2006-01-03
申请人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
发明人： Ta-Chuan Yeh , Ni-Min Chung , Kao-Su Huang , Yung-Chang Lin , Ruey-Chyr Lee , Chien-Kuo Wang
IPC分类号： H01L21/20
CPC分类号： H01L27/1087 , H01L21/76205
摘要： A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is filled in the deep trench opening.
摘要翻译：提供了具有氧化物层，第一氮化硅 - 硅，STI和第二氮化硅 - 硅的衬底。蚀刻第二氮化硅 - 硅层上的图案多晶硅层以形成深沟槽开口。蚀刻图案多晶硅层也加深了深沟槽开口。然后，在深沟槽开口中填充导电层。

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