专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090079460A1 SYSTEMS AND METHOD FOR MEASURING NEGATIVE BIAS THERMAL INSTABILITY WITH A RING OSCILLATOR 有权
标题翻译：用环形振荡器测量负偏差热不稳定性的系统和方法
公开(公告)号：US20090079460A1
公开(公告)日：2009-03-26
申请号：US12277227
申请日：2008-11-24
申请人： Shingo Suzuki
发明人： Shingo Suzuki
IPC分类号： G01R31/28
CPC分类号： G01R31/129 , G01R31/31924
摘要： An integrated circuit, in accordance with one embodiment of the present invention, includes a first device under test (DUT), a first ring oscillator, a second DUT and a second ring oscillator. The first DUT is biased such that interface traps are generated during a first mode. The generated interface traps result in a decrease in a first drive current of the first DUT. The second device under test is biased to maintain a reference drive current during the first mode. The operating frequency of the first ring oscillator, during a second mode, is a function of the first drive current. The operating frequency of the second ring oscillator, during the second mode, is a function of the reference drive current. The integrated circuit may also include a comparator for generating an output signal as a function of a difference between the operating frequency of the first and second ring oscillator.
摘要翻译：根据本发明的一个实施例的集成电路包括被测试的第一器件（DUT），第一环形振荡器，第二DUT和第二环形振荡器。第一DUT被偏置，使得在第一模式期间产生接口陷阱。所产生的接口陷阱导致第一DUT的第一驱动电流的减小。被测试的第二器件被偏置以在第一模式期间保持参考驱动电流。在第二模式期间，第一环形振荡器的工作频率是第一驱动电流的函数。在第二模式期间，第二环形振荡器的工作频率是参考驱动电流的函数。集成电路还可以包括用于产生作为第一和第二环形振荡器的工作频率之间的差的函数的输出信号的比较器。

2. 发明授权

US07509504B1 Systems and methods for control of integrated circuits comprising body biasing systems 有权
标题翻译：包括主体偏置系统的集成电路的控制系统和方法
公开(公告)号：US07509504B1
公开(公告)日：2009-03-24
申请号：US10956219
申请日：2004-09-30
申请人： Kleanthes G. Koniaris , Stephen Lee , Mark Hennecke
发明人： Kleanthes G. Koniaris , Stephen Lee , Mark Hennecke
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3231 , Y02D10/173
摘要： Systems and methods for control of integrated circuits comprising body-biasing systems. In accordance with a first embodiment of the present invention, a desirable power condition of a computer system comprising a microprocessor is determined. Body biasing voltage information corresponding to the power condition is accessed. A voltage supply coupled to a body terminal of the microprocessor is commanded to generate a voltage corresponding to the body biasing voltage information corresponding to the power condition.
摘要翻译：包括主体偏置系统的集成电路的控制系统和方法。根据本发明的第一实施例，确定包括微处理器的计算机系统的期望功率条件。访问与功率条件相对应的主体偏置电压信息。命令耦合到微处理器的主体端子的电压源产生对应于与电源状态对应的主体偏置电压信息的电压。

3. 发明授权

US07495497B1 Temperature compensated integrated circuits 有权
标题翻译：温度补偿集成电路
公开(公告)号：US07495497B1
公开(公告)日：2009-02-24
申请号：US11125555
申请日：2005-05-09
申请人： Robert Fu
发明人： Robert Fu
IPC分类号： H03K17/687
CPC分类号： H03K19/00384 , H03K3/011 , H03K3/0315 , H03K17/145
摘要： A method and system of temperature compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of temperature compensation.
摘要翻译：温度补偿集成电路的方法和系统。通过应用温度补偿来增强集成电路的工作特性。

4. 发明授权

US07478226B1 Processing bypass directory tracking system and method 有权
标题翻译：处理旁路目录跟踪系统和方法
公开(公告)号：US07478226B1
公开(公告)日：2009-01-13
申请号：US11540789
申请日：2006-09-29
申请人： Alexander Klaiber , Guillermo Rozas
发明人： Alexander Klaiber , Guillermo Rozas
IPC分类号： G06F9/34
CPC分类号： G06F9/3838 , G06F9/30134 , G06F9/3826 , G06F9/384
摘要： A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at.
摘要翻译：公开了一种处理旁路目录系统和方法。在一个实施例中，旁路目录跟踪处理包括在写入对应的体系结构寄存器时在旁路目录中设置位。每个周期在旁路目录中选择性地清零这些位。利用这些位的配置来确定旁路路径处理信息的哪个阶段。

5. 发明申请

US20080313440A1 SWITCHING TO ORIGINAL CODE COMPARISON OF MODIFIABLE CODE FOR TRANSLATED CODE VALIDITY WHEN FREQUENCY OF DETECTING MEMORY OVERWRITES EXCEEDS THRESHOLD 失效
标题翻译：当检测到内存超过阈值的频率超过阈值时，切换到转换代码有效性的可修改代码的原始代码比较
公开(公告)号：US20080313440A1
公开(公告)日：2008-12-18
申请号：US12177836
申请日：2008-07-22
申请人： John Banning , H. Peter Anvin , Robert Bedicheck , Guillermo J. Rozas , Andrew Shaw , Linus Torvalds , Jason Wilson
发明人： John Banning , H. Peter Anvin , Robert Bedicheck , Guillermo J. Rozas , Andrew Shaw , Linus Torvalds , Jason Wilson
IPC分类号： G06F9/315
CPC分类号： G06F9/3808 , G06F9/3812
摘要： A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.
摘要翻译：将指令从目标指令集转换为主机指令集的方法。在一个实施例中，多个第一目标指令被转换成多个第一主机指令。在翻译之后，确定多个第一目标指令是否已改变。如果确定减慢了计算机系统的操作，则存储第二多个目标指令的副本并与多个第一目标指令进行比较。在比较之后，如果存在不匹配，则多个第一主机指令被无效。根据一个实施例，当确定指示页面包含对多个第一目标指令的至少一个改变时，开始存储，比较和无效。在一个实施例中，确定是通过检查与多个第一目标指令的存储器位置相关联的比特指示符。

6. 发明申请

US20080303600A1 Dynamic Ring Oscillators 有权
标题翻译：动态振荡器
公开(公告)号：US20080303600A1
公开(公告)日：2008-12-11
申请号：US12194504
申请日：2008-08-19
申请人： Robert P. Masleid
发明人： Robert P. Masleid
IPC分类号： H03B5/24
CPC分类号： H03K3/0315
摘要： A dynamic oscillating ring circuit is described, which has multiple non-inverting domino circuits, each having a signal input, a trigger input, inputs for charge state clock and clocked cutoff and an output inverter. A number of the domino circuits are coupled in series, the output of one feeding the input of the next, to form a chain, which form stages of the ring. A number of the stages are coupled in series, the output of one feeding the input of the next, to form the ring. The first domino circuit of said chain receives a logic signal input and a single trigger input for the chain. Within the ring, the output of each stage feeds the input signal to the next stage and is fed back to clock an earlier stage to allow the ring to oscillate.
摘要翻译：描述了一种动态振荡环电路，其具有多个反相多米诺骨架电路，每个具有信号输入，触发输入，充电状态时钟和时钟截止的输入以及输出反相器。一些多米诺骨牌电路是串联耦合的，一个输出端输入下一个输入端，形成一个链，形成环的阶段。多个阶段串联耦合，输出一个馈入下一个输入，形成环。所述链的第一个多米诺骨牌电路接收逻辑信号输入和单个触发输入。在环内，每个级的输出将输入信号馈送到下一级，并将其反馈到时钟的较早阶段以允许环振荡。

7. 发明授权

US07463050B1 System and method for controlling temperature during burn-in 有权
标题翻译：老化期间控制温度的系统和方法
公开(公告)号：US07463050B1
公开(公告)日：2008-12-09
申请号：US11139116
申请日：2005-05-26
申请人： Eric Chen-Li Sheng , David H. Hoffman , John Laurence Niven
发明人： Eric Chen-Li Sheng , David H. Hoffman , John Laurence Niven
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/2817
摘要： Systems and methods for reducing temperature dissipation during burn-in testing are described. Devices under test are each subject to a body bias voltage. The body bias voltage can be used to control junction temperature (e.g., temperature measured at the device under test). The body bias voltage applied to each device under test can be adjusted device-by-device to achieve essentially the same junction temperature at each device.
摘要翻译：描述了在老化测试期间降低温度耗散的系统和方法。被测器件每个都受到体偏置电压的影响。体偏置电压可用于控制结温（例如，在被测器件测量的温度）。施加到每个待测器件的体偏置电压可以逐个设备调整，以在每个器件上达到基本上相同的结温。

8. 发明授权

US07456628B2 System and method for measuring negative bias thermal instability with a ring oscillator 有权
标题翻译：用环形振荡器测量负偏置热不稳定性的系统和方法
公开(公告)号：US07456628B2
公开(公告)日：2008-11-25
申请号：US12006473
申请日：2008-01-02
申请人： Shingo Suzuki
发明人： Shingo Suzuki
IPC分类号： G01R31/28
CPC分类号： G01R31/129 , G01R31/31924
摘要： An integrated circuit, in accordance with one embodiment of the present invention, includes a first device under test (DUT), a first ring oscillator, a second DUT and a second ring oscillator. The first DUT is biased such that interface traps are generated during a first mode. The generated interface traps result in a decrease in a first drive current of the first DUT. The second device under test is biased to maintain a reference drive current during the first mode. The operating frequency of the first ring oscillator, during a second mode, is a function of the first drive current. The operating frequency of the second ring oscillator, during the second mode, is a function of the reference drive current. The integrated circuit may also include a comparator for generating an output signal as a function of a difference between the operating frequency of the first and second ring oscillator.
摘要翻译：根据本发明的一个实施例的集成电路包括被测试的第一器件（DUT），第一环形振荡器，第二DUT和第二环形振荡器。第一DUT被偏置，使得在第一模式期间产生接口陷阱。所产生的接口陷阱导致第一DUT的第一驱动电流的减小。被测试的第二器件被偏置以在第一模式期间保持参考驱动电流。在第二模式期间，第一环形振荡器的工作频率是第一驱动电流的函数。在第二模式期间，第二环形振荡器的工作频率是参考驱动电流的函数。集成电路还可以包括用于产生作为第一和第二环形振荡器的工作频率之间的差的函数的输出信号的比较器。

9. 发明申请

US20080135905A1 SELECTIVE COUPLING OF VOLTAGE FEEDS FOR BODY BIAS VOLTAGE IN AN INTEGRATED CIRCUIT DEVICE 有权
标题翻译：用于集成电路设备中的身体偏置电压的电压馈电的选择性耦合
公开(公告)号：US20080135905A1
公开(公告)日：2008-06-12
申请号：US12033840
申请日：2008-02-19
申请人： James B. Burr , Robert Fu
发明人： James B. Burr , Robert Fu
IPC分类号： H01L23/50 , G11C5/14
CPC分类号： H01L29/0646 , G11C5/146 , H01L21/823493 , H01L21/823892 , H01L23/481 , H01L27/0203 , H01L27/0222 , H01L27/0928 , H01L29/1095 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.
摘要翻译：一种具有体偏置电压机构的集成电路器件。集成电路包括设置在其中的电阻结构，用于选择性地将外部体偏置电压或电源电压耦合到偏置阱。可以可选地提供用于与第一外部设置的销连接的第一垫。第一个焊盘用于接收外部施加的主体偏置电压。用于产生体偏置电压的电路可以耦合到第一焊盘，用于将体偏置电压耦合到设置在集成电路器件上的多个偏置阱。如果没有提供外部施加的体偏置电压，则电阻结构自动将电源电压耦合到偏置阱。电源电压可以在集成电路内部获得。

10. 发明授权

US07380096B1 System and method for identifying TLB entries associated with a physical address of a specified range 有权
标题翻译：用于识别与指定范围的物理地址相关联的TLB条目的系统和方法
公开(公告)号：US07380096B1
公开(公告)日：2008-05-27
申请号：US11449950
申请日：2006-06-08
申请人： Guillermo Rozas , Alexander Klaiber , H. Peter Anvin , David Dunn
发明人： Guillermo Rozas , Alexander Klaiber , H. Peter Anvin , David Dunn
IPC分类号： G06F12/00
CPC分类号： G06F12/1054
摘要： A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.
摘要翻译：公开了一种用于识别具有在指定范围内的物理地址的TLB条目的系统和方法。该方法包括从页表条目获取暂定TLB条目并访问与暂定TLB条目相关联的物理地址。该方法还包括将暂定TLB条目的物理地址与预定范围的地址进行比较。如果物理地址在有限的地址范围内，则会调用异常。响应于异常，可以修改临时TLB条目的物理地址和/或属性。然后可以将暂定的TLB条目存储在TLB中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式