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1. 发明申请

US20220365416A1 EXTREME ULTRAVIOLET LIGHT REFLECTIVE STRUCTURE INCLUDING NANO-LATTICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20220365416A1
公开(公告)日：2022-11-17
申请号：US17875385
申请日：2022-07-27
申请人： TAIWAN SEMICONDUCTOR MAUFACTURING COMPANY, LTD.
发明人： Benny KU , Keith Kuang-Kuo KOAI , Wen-Hao CHENG
IPC分类号： G03F1/24
摘要： An EUV reflective structure includes a substrate and multiple pairs of a Si layer and a Mo layer. The Si layer includes a plurality of cavities.

2. 发明授权

US08969913B2 Insulated gate bipolar transistor structure having low substrate leakage 有权
标题翻译：具有低衬底泄漏的绝缘栅双极晶体管结构
公开(公告)号：US08969913B2
公开(公告)日：2015-03-03
申请号：US13673734
申请日：2012-11-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ker Hsiao Huo , Chih-Chang Cheng , Ru-Yi Su , Jen-Hao Yeh , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L29/66
CPC分类号： H01L29/7816 , H01L21/265 , H01L29/0646 , H01L29/0696 , H01L29/1033 , H01L29/1083 , H01L29/1095 , H01L29/66325 , H01L29/66681 , H01L29/7393
摘要： A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well.
摘要翻译：在本公开中提供了高压横向扩散的金属氧化物半导体（HV LDMOS）器件，特别是绝缘栅双极结型晶体管（IGBT）及其制造方法。该器件包括具有至少一个高掺杂掩埋部分的半导体衬底，在衬底上生长的第一掺杂阱，形成在第一阱上的栅极结构，形成在栅极结构的任一侧的源极和漏极，在第一阱中形成具有U形横截面的掺杂阱。排水口的一部分形成在第二井外部的第一井上。

3. 发明申请

US20140264478A1 INTERFACE FOR METAL GATE INTEGRATION 有权
标题翻译：金属门整合界面
公开(公告)号：US20140264478A1
公开(公告)日：2014-09-18
申请号：US13796576
申请日：2013-03-12
申请人： Taiwan Semiconductor Maufacturing Company, Ltd.
发明人： Jinn-Kwei Liang , Chung-Ren Sun , Shiu-Ko Jang Jiang , Hsiang-Hsiang Ko
IPC分类号： H01L29/78 , H01L21/28 , H01L29/66
CPC分类号： H01L21/28079 , H01L21/28088 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： A metal oxide semiconductor field effect transistor (MOSFET) includes a semiconductor substrate and a interlayer dielectric (ILD) over the semiconductor substrate. A gate structure is formed within the ILD and disposed on the semiconductor substrate, wherein the gate structure includes a high-k dielectric material layer and a metal gate stack. One or more portions of a protection layer are formed over the gate stack, and a contact etch stop layer is formed over the ILD and over the one or more portions of the protection layer. The metal gate stack includes aluminum and the protection layer includes aluminum oxide.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）包括在半导体衬底上的半导体衬底和层间电介质（ILD）。栅极结构形成在ILD内并且设置在半导体衬底上，其中栅极结构包括高k电介质材料层和金属栅叠层。保护层的一个或多个部分形成在栅极叠层上，并且接触蚀刻停止层形成在ILD上方以及保护层的一个或多个部分之上。金属栅堆叠包括铝，保护层包括氧化铝。

4. 发明公开

US20230375909A1 EXTREME ULTRAVIOLET LIGHT REFLECTIVE STRUCTURE INCLUDING NANO-LATTICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20230375909A1
公开(公告)日：2023-11-23
申请号：US18227866
申请日：2023-07-28
申请人： TAIWAN SEMICONDUCTOR MAUFACTURING COMPANY, LTD.
发明人： Benny KU , Keith Kuang-Kuo KOAI , Wen-Hao CHENG
IPC分类号： G03F1/24
CPC分类号： G03F1/24
摘要： An EUV reflective structure includes a substrate and multiple pairs of a Si layer and a Mo layer. The Si layer includes a plurality of cavities.

5. 发明授权

US08487382B2 Device scheme of HKMG gate-last process 有权
标题翻译： HKMG最终进程的设备方案
公开(公告)号：US08487382B2
公开(公告)日：2013-07-16
申请号：US13292665
申请日：2011-11-09
申请人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/70
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/66545
摘要： The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.
摘要翻译：本公开提供了制造半导体器件的金属栅叠层的方法。该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成导电材料层; 在n型场效应晶体管（nFET）区域中形成伪栅极，在使用多晶硅的pFET区域中形成第二伪栅极; 在所述半导体衬底上形成层间电介质（ILD）材料; 对半导体衬底施加第一化学机械抛光（CMP）工艺; 从第一伪栅极去除多晶硅，产生第一栅极沟槽; 在第一栅极沟槽上形成n型金属; 对所述半导体衬底施加第二CMP工艺; 从第二伪栅极去除多晶硅，产生第二栅极沟槽; 在所述第二栅极沟槽中形成p型金属; 以及对所述半导体衬底施加第三CMP处理。

6. 发明申请

US20100102411A1 PHOTODETECTOR FOR BACKSIDE-ILLUMINATED SENSOR 有权
标题翻译：背光照明传感器的光电二极管
公开(公告)号：US20100102411A1
公开(公告)日：2010-04-29
申请号：US12651236
申请日：2009-12-31
申请人： Tzu-Hsuan Hsu , Dun-Nian Yaung , Ching-Chun Wang
发明人： Tzu-Hsuan Hsu , Dun-Nian Yaung , Ching-Chun Wang
IPC分类号： H01L31/00 , H01L31/062
CPC分类号： H01L27/14643 , H01L27/14625 , H01L27/1464
摘要： A backside-illuminated sensor including a semiconductor substrate. The semiconductor substrate has a front surface and a back surface. A plurality of pixels are formed on the front surface of the semiconductor substrate. At least one pixel includes a photogate structure. The photogate structure has a metal gate that includes a reflective layer.
摘要翻译：背面照明传感器，包括半导体衬底。半导体衬底具有前表面和后表面。在半导体衬底的前表面上形成多个像素。至少一个像素包括光栅结构。光栅结构具有包括反射层的金属栅极。

7. 发明申请

US20120169409A1 CHARGE PUMP CIRCUITS, SYSTEMS, AND OPERATIONAL METHODS THEREOF 有权
标题翻译：充电泵电路，系统及其操作方法
公开(公告)号：US20120169409A1
公开(公告)日：2012-07-05
申请号：US13417016
申请日：2012-03-09
申请人： Ming-Dou KER , Yi-Hsin WENG
发明人： Ming-Dou KER , Yi-Hsin WENG
IPC分类号： G05F3/02
CPC分类号： H02M3/073 , G11C5/145 , H02M2003/075 , H02M2003/077
摘要： A charge pump circuit includes at least one stage between an input end and an output end. The at least one stage includes a first CMOS transistor coupled with a first capacitor and a second CMOS transistor coupled with a second capacitor. The at least one stage is capable of receiving a first timing signal and a second timing signal for pumping an input voltage at the input end to an output voltage at the output end. During a transitional period of the first timing signal and the second timing signal, the at least one stage is capable of substantially turning off at least one of the first CMOS transistor and the second CMOS transistor for substantially reducing leakage currents flowing through at least one of the first CMOS transistor and the second CMOS transistor.
摘要翻译：电荷泵电路包括在输入端和输出端之间的至少一个级。所述至少一个级包括与第一电容器耦合的第一CMOS晶体管和与第二电容器耦合的第二CMOS晶体管。所述至少一个级能够接收第一定时信号和第二定时信号，用于将输入端的输入电压泵送到输出端的输出电压。在第一定时信号和第二定时信号的过渡时段期间，至少一个级能够基本上关闭第一CMOS晶体管和第二CMOS晶体管中的至少一个，用于基本上减少流过至少一个第一CMOS晶体管和第二CMOS晶体管。

8. 发明申请

US20110027944A1 METHOD OF FORMING ELECTRICAL CONNECTIONS 有权
标题翻译：形成电气连接的方法
公开(公告)号：US20110027944A1
公开(公告)日：2011-02-03
申请号：US12768025
申请日：2010-04-27
申请人： Chung-Shi LIU , Shin-Puu JENG , Mirng-Ji LII , Chen-Hua YU
发明人： Chung-Shi LIU , Shin-Puu JENG , Mirng-Ji LII , Chen-Hua YU
IPC分类号： H01L21/768 , H01L21/56
CPC分类号： H01L23/3171 , H01L21/563 , H01L23/525 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/10126 , H01L2224/1147 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/73203 , H01L2924/00013 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2224/13099
摘要： A method of forming electrical connections to a semiconductor wafer. A semiconductor wafer comprising an insulation layer is provided. The insulation layer has a surface. A patterned mask layer is formed over the surface of the insulation layer. The patterned mask layer exposes portions of the surface of the insulation layer through a plurality of holes. The portions of the plurality of holes are filled with a metal material comprising copper to form elongated columns of the metal material. The elongated columns of the metal material have a sidewall surface. The patterned mask layer is removed to expose the sidewall surface of the elongated columns of the metal material. A protection layer is formed on the exposed sidewall surface of the elongated columns of the metal material.
摘要翻译：形成与半导体晶片的电连接的方法。提供了包括绝缘层的半导体晶片。绝缘层具有表面。在绝缘层的表面上形成图案化掩模层。图案化掩模层通过多个孔暴露绝缘层的表面的部分。多个孔的部分填充有包含铜的金属材料以形成细长的金属材料柱。金属材料的细长柱具有侧壁表面。去除图案化的掩模层以暴露金属材料的细长柱的侧壁表面。保护层形成在金属材料的细长柱的暴露的侧壁表面上。

9. 发明授权

US08434032B2 Method of generating an intellectual property block design kit, method of generating an integrated circuit design, and simulation system for the integrated circuit design 有权
标题翻译：生成知识产权块设计套件的方法，集成电路设计的生成方法和集成电路设计的仿真系统
公开(公告)号：US08434032B2
公开(公告)日：2013-04-30
申请号：US12950371
申请日：2010-11-19
申请人： Lee-Chung Lu , Yun-Han Lee , Wei-Li Chen , Tan-Li Chou , Kheng-Guan Tan , Shi-Hung Wang
发明人： Lee-Chung Lu , Yun-Han Lee , Wei-Li Chen , Tan-Li Chou , Kheng-Guan Tan , Shi-Hung Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F2217/02 , G06F2217/66
摘要： The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit.
摘要翻译：本申请公开了一种生成包括IP块电路设计和用于制造集成电路的系统级特性表的知识产权（IP）块设计套件的方法。根据至少一个实施例，产生IP块电路设计。 IP块电路设计基于预定的配置集进行仿真，每个配置集都具有制造选项和/或操作条件。基于IP块电路设计的仿真，生成用于预定配置集的多个系统级模型。通过根据系统级特征建模设备的系统级特征表模板布置预定配置集和系统级模型来生成系统级特征表。然后将IP块电路设计和系统级特性表存储为IP块设计工具包。

10. 发明授权

US07871923B2 Self-aligned air-gap in interconnect structures 有权
标题翻译：互连结构中的自对准气隙
公开(公告)号：US07871923B2
公开(公告)日：2011-01-18
申请号：US11698565
申请日：2007-01-26
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure comprising an air gap and methods for forming the same are provided. The integrated circuit structure includes a conductive line; a self-aligned dielectric layer on a sidewall of the conductive line; an air-gap horizontally adjoining the self-aligned dielectric layer; a low-k dielectric layer horizontally adjoining the air-gap; and a dielectric layer on the air-gap and the low-k dielectric layer.
摘要翻译：提供一种包括气隙的集成电路结构及其形成方法。集成电路结构包括导线; 在导电线的侧壁上的自对准电介质层; 水平地邻接所述自对准介电层的气隙; 水平地邻接气隙的低k电介质层; 以及气隙和低k电介质层上的电介质层。

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