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1. 发明申请

US20130125393A1 FLIP CHIP PACKAGE FOR MONOLITHIC SWITCHING REGULATOR 有权
标题翻译：用于单片开关稳压器的FLIP芯片封装
公开(公告)号：US20130125393A1
公开(公告)日：2013-05-23
申请号：US13740405
申请日：2013-01-14
申请人： Silergy Technology
发明人： Budong You
IPC分类号： H05K3/34
CPC分类号： H05K3/341 , H01L23/3107 , H01L23/49548 , H01L23/49562 , H01L23/49572 , H01L24/16 , H01L24/17 , H01L2224/16245 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , Y10T29/49144 , H01L2924/00
摘要： Methods and apparatuses related to packaging a monolithic voltage regulator are disclosed. In one embodiment, an apparatus includes: (i) a monolithic voltage regulator with a transistor arranged as parallel transistor devices; (ii) bumps on the monolithic voltage regulator to form connections to source and drain terminals of the transistor; (iii) a single layer lead frame with a plurality of interleaving lead fingers coupled to the monolithic voltage regulator via the bumps, where the single layer lead frame includes first and second surfaces, where the first surface includes a first pattern to form connections to the bumps, and where the second surface includes a second pattern that is different from the first pattern; and (iv) a flip-chip package encapsulating the monolithic voltage regulator, the bumps, and the single layer lead frame, where the flip-chip package has external connectors of the monolithic voltage regulator at the second surface of the single layer lead frame.
摘要翻译：公开了与封装单片电压调节器相关的方法和装置。在一个实施例中，一种装置包括：（i）具有被设置为并行晶体管器件的晶体管的单片电压调节器; （ii）单片电压调节器上的凸块以形成到晶体管的源极和漏极端子的连接; （iii）单层引线框架，其具有经由所述凸块耦合到所述单片电压调节器的多个交错引线，其中所述单层引线框架包括第一和第二表面，其中所述第一表面包括第一图案以形成到所述并且其中第二表面包括不同于第一图案的第二图案; 以及（iv）封装单片稳压器，凸块和单层引线框架的倒装芯片封装，其中倒装芯片封装在单层引线框架的第二表面处具有单片稳压器的外部连接器。

2. 发明授权

US08400784B2 Flip chip package for monolithic switching regulator 有权
标题翻译：用于单片开关稳压器的倒装芯片封装
公开(公告)号：US08400784B2
公开(公告)日：2013-03-19
申请号：US12462839
申请日：2009-08-10
申请人： Budong You
发明人： Budong You
IPC分类号： H05K5/02
CPC分类号： H05K3/341 , H01L23/3107 , H01L23/49548 , H01L23/49562 , H01L23/49572 , H01L24/16 , H01L24/17 , H01L2224/16245 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , Y10T29/49144 , H01L2924/00
摘要： Methods and apparatuses related to packaging a monolithic voltage regulator are disclosed. In one embodiment, an apparatus includes: (i) a monolithic voltage regulator with a transistor arranged as parallel transistor devices; (ii) bumps on the monolithic voltage regulator to form connections to source and drain terminals of the transistor; (iii) a single layer lead frame with a plurality of interleaving lead fingers coupled to the monolithic voltage regulator via the bumps, where the single layer lead frame includes first and second surfaces, where the first surface includes a first pattern to form connections to the bumps, and where the second surface includes a second pattern that is different from the first pattern; and (iv) a flip-chip package encapsulating the monolithic voltage regulator, the bumps, and the single layer lead frame, where the flip-chip package has external connectors of the monolithic voltage regulator at the second surface of the single layer lead frame.
摘要翻译：公开了与封装单片电压调节器相关的方法和装置。在一个实施例中，一种装置包括：（i）具有被设置为并行晶体管器件的晶体管的单片电压调节器; （ii）单片电压调节器上的凸块以形成到晶体管的源极和漏极端子的连接; （iii）单层引线框架，其具有经由所述凸块耦合到所述单片电压调节器的多个交错引线，其中所述单层引线框架包括第一和第二表面，其中所述第一表面包括第一图案以形成到所述并且其中第二表面包括不同于第一图案的第二图案; 以及（iv）封装单片稳压器，凸块和单层引线框架的倒装芯片封装，其中倒装芯片封装在单层引线框架的第二表面处具有单片稳压器的外部连接器。

3. 发明申请

US20130015523A1 FABRICATION OF LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) DEVICES 有权
标题翻译：侧面双向扩散金属氧化物半导体（LDMOS）器件的制造
公开(公告)号：US20130015523A1
公开(公告)日：2013-01-17
申请号：US13332700
申请日：2011-12-21
申请人： Budong You
发明人： Budong You
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L21/823814 , H01L21/823892 , H01L27/0922 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions.
摘要翻译：公开了横向双扩散金属氧化物半导体（LDMOS）晶体管的制造，结构，器件和/或应用的方法。在一个实施例中，制造在衬底上具有源极，漏极和栅极区域的LDMOS晶体管的方法可以包括：形成p型和n型掩埋层（PBL，NBL）区域; 在NBL / PBL区域生长外延（N-EPI）层; 在PBL区上形成p掺杂的深p阱（DPW）区域; 在N-EPI层中形成阱区; 形成掺杂的体区; 形成有源区和场氧化物（FOX）区，并在LDMOS晶体管的源极和漏极区之间形成漏极氧化物; 形成与源极和漏极相邻的栅极氧化物，以及在栅极氧化物和一部分漏极氧化物上形成栅极; 以及形成掺杂漏极区，以及第一和第二掺杂源极区。

4. 发明授权

US08138049B2 Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices 有权
标题翻译：横向双扩散金属氧化物半导体（LDMOS）器件的制造
公开(公告)号：US08138049B2
公开(公告)日：2012-03-20
申请号：US12455223
申请日：2009-05-29
申请人： Budong You
发明人： Budong You
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/823814 , H01L21/823892 , H01L27/0922 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; after the doped body region formation, forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; after the doped body region formation, forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions.
摘要翻译：公开了横向双扩散金属氧化物半导体（LDMOS）晶体管的制造，结构，器件和/或应用的方法。在一个实施例中，制造在衬底上具有源极，漏极和栅极区域的LDMOS晶体管的方法可以包括：形成p型和n型掩埋层（PBL，NBL）区域; 在NBL / PBL区域生长外延（N-EPI）层; 在PBL区上形成p掺杂的深p阱（DPW）区域; 在N-EPI层中形成阱区; 形成掺杂体区域; 在掺杂体区形成之后，形成有源区和场氧化物（FOX）区，并在LDMOS晶体管的源极和漏极区之间形成漏极氧化物; 在掺杂体区域形成之后，形成与源极和漏极区域相邻的栅极氧化物，并在栅极氧化物和一部分漏极氧化物上形成栅极; 以及形成掺杂漏极区，以及第一和第二掺杂源极区。

5. 发明授权

US08119507B2 Lateral double-diffused metal oxide semiconductor (LDMOS) transistors 有权
标题翻译：横向双扩散金属氧化物半导体（LDMOS）晶体管
公开(公告)号：US08119507B2
公开(公告)日：2012-02-21
申请号：US12288836
申请日：2008-10-23
申请人： Budong You
发明人： Budong You
IPC分类号： H01L21/425 , H01L21/336 , H01L29/66 , H01L27/088
CPC分类号： H01L29/0878 , H01L29/086 , H01L29/42368 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66689 , H01L29/7816
摘要： Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region.
摘要翻译：公开了横向双扩散金属氧化物半导体（LDMOS）晶体管的制造，结构，器件和/或应用的方法。在一个实施例中，LDMOS晶体管可以包括：（i）衬底上的n掺杂的深n阱（DNW）区域; （ii）在所述LDMOS晶体管的源极区域和漏极区域之间的栅极氧化物和漏极氧化物，所述栅极氧化物与所述源极区域相邻，所述漏极氧化物与所述漏极区域相邻; （iii）栅极氧化物上的导电栅极和漏极氧化物的一部分; （iv）源极区中的p掺杂p体区域; （v）漏区中的n掺杂漏极区; （vi）源区域的p掺杂p体区域中与其相邻的第一n掺杂n +区域和p掺杂p +区域; 和（vii）漏区中的第二n掺杂n +区。

6. 发明授权

US08912600B2 Lateral double-diffused metal oxide semiconductor (LDMOS) transistors 有权
标题翻译：横向双扩散金属氧化物半导体（LDMOS）晶体管
公开(公告)号：US08912600B2
公开(公告)日：2014-12-16
申请号：US13331230
申请日：2011-12-20
申请人： Budong You
发明人： Budong You
IPC分类号： H01L29/78 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/51
CPC分类号： H01L29/0878 , H01L29/086 , H01L29/42368 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66689 , H01L29/7816
摘要： Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region.
摘要翻译：公开了横向双扩散金属氧化物半导体（LDMOS）晶体管的制造，结构，器件和/或应用的方法。在一个实施例中，LDMOS晶体管可以包括：（i）衬底上的n掺杂的深n阱（DNW）区域; （ii）在所述LDMOS晶体管的源极区域和漏极区域之间的栅极氧化物和漏极氧化物，所述栅极氧化物与所述源极区域相邻，所述漏极氧化物与所述漏极区域相邻; （iii）栅极氧化物上的导电栅极和漏极氧化物的一部分; （iv）源极区中的p掺杂p体区域; （v）漏区中的n掺杂漏极区; （vi）源区域的p掺杂p体区域中与其相邻的第一n掺杂n +区域和p掺杂p +区域; 和（vii）漏区中的第二n掺杂n +区。

7. 发明申请

US20120153922A1 CONTROL FOR REGULATOR FAST TRANSIENT RESPONSE AND LOW EMI NOISE 有权
标题翻译：控制调节器快速瞬态响应和低EMI噪声
公开(公告)号：US20120153922A1
公开(公告)日：2012-06-21
申请号：US13397920
申请日：2012-02-16
申请人： Wei Chen , Michael Grimm
发明人： Wei Chen , Michael Grimm
IPC分类号： G05F1/46
CPC分类号： H02M3/1563 , H02M3/156 , H02M2001/0025
摘要： Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a switching regulator can include: (i) a filter network coupled to an output terminal, where an output voltage is generated at the output terminal from an input source; (ii) an active switch to connect the input source to the filter network by periodically operating between on and off states over a switching period, where a duty cycle of the on state relative to the switching period is modulated based on a PWM control signal; (iii) a comparator receiving an output feedback signal, a hysteresis signal, and a reference level, and providing the PWM control signal therefrom; and (iv) a hysteresis programming circuit generating the hysteresis signal, and a ramp control signal, where the hysteresis signal is programmed based on conditions at the input source and the output voltage to achieve a pseudo constant frequency operation.
摘要翻译：本文公开了用于电源布置和控制的方法和电路。在一个实施例中，开关调节器可以包括：（i）耦合到输出端子的滤波器网络，其中在输出端子处从输入源产生输出电压; （ii）有源开关，其通过在开关周期内周期性地在导通和截止状态之间工作来连接输入源到滤波器网络，其中基于PWM控制信号调制导通状态相对于开关周期的占空比; （iii）比较器，其接收输出反馈信号，滞后信号和参考电平，并从其提供PWM控制信号; 以及（iv）产生滞后信号的滞后编程电路和斜坡控制信号，其中基于输入源和输出电压的条件对迟滞信号进行编程，以实现伪恒频操作。

8. 发明授权

US08169205B2 Control for regulator fast transient response and low EMI noise 有权
公开(公告)号：US08169205B2
公开(公告)日：2012-05-01
申请号：US12454875
申请日：2009-05-26
申请人： Wei Chen , Michael Grimm
发明人： Wei Chen , Michael Grimm
IPC分类号： G05F1/00
CPC分类号： H02M3/1563 , H02M3/156 , H02M2001/0025
摘要： Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a switching regulator can include: (i) a filter network coupled to an output terminal, where an output voltage is generated at the output terminal from an input source; (ii) an active switch to connect the input source to the filter network by periodically operating between on and off states over a switching period, where a duty cycle of the on state relative to the switching period is modulated based on a PWM control signal; (iii) a comparator receiving an output feedback signal, a hysteresis signal, and a reference level, and providing the PWM control signal therefrom; and (iv) a hysteresis programming circuit generating the hysteresis signal, and a ramp control signal, where the hysteresis signal is programmed based on conditions at the input source and the output voltage to achieve a pseudo constant frequency operation.

9. 发明申请

US20120091527A1 LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) TRANSISTORS 有权
标题翻译：侧向双向扩散金属氧化物半导体（LDMOS）晶体管
公开(公告)号：US20120091527A1
公开(公告)日：2012-04-19
申请号：US13331230
申请日：2011-12-20
申请人： Budong You
发明人： Budong You
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L29/086 , H01L29/42368 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66689 , H01L29/7816
摘要： Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region.
摘要翻译：公开了横向双扩散金属氧化物半导体（LDMOS）晶体管的制造，结构，器件和/或应用的方法。在一个实施例中，LDMOS晶体管可以包括：（i）衬底上的n掺杂的深n阱（DNW）区域; （ii）在所述LDMOS晶体管的源极区域和漏极区域之间的栅极氧化物和漏极氧化物，所述栅极氧化物与所述源极区域相邻，所述漏极氧化物与所述漏极区域相邻; （iii）栅极氧化物上的导电栅极和漏极氧化物的一部分; （iv）源极区中的p掺杂p体区域; （v）漏区中的n掺杂漏极区; （vi）源区域的p掺杂p体区域中与其相邻的第一n掺杂n +区域和p掺杂p +区域; 和（vii）漏区中的第二n掺杂n +区。

10. 发明授权

US08067925B2 Hybrid power converter 有权
标题翻译：混合动力转换器
公开(公告)号：US08067925B2
公开(公告)日：2011-11-29
申请号：US12313457
申请日：2008-11-20
申请人： Michael Grimm
发明人： Michael Grimm
IPC分类号： G05F1/40
CPC分类号： H02M3/156 , H02M1/32 , H02M2001/0045
摘要： Power converter circuits, structures, and methods are disclosed herein. In one embodiment, a hybrid converter can include: (i) a first switching device controllable by a control signal; (ii) an inductor coupled to the first switching device and an output; and (iii) a control circuit configured to receive feedback from the output for generation of the control signal to control the first switching device, where the control circuit includes a first detection circuit configured to detect first and second output conditions, the control circuit being configured to operate the first switching device in a switch control in response to the control signal when the first output condition is detected, and to operate the first switching device in a linear control region when the second output condition is detected.
摘要翻译：本文公开了功率转换器电路，结构和方法。在一个实施例中，混合转换器可以包括：（i）可由控制信号控制的第一开关装置; （ii）耦合到所述第一开关装置的电感器和输出端; 以及（iii）控制电路，被配置为从所述输出接收用于产生所述控制信号的反馈以控制所述第一开关器件，其中所述控制电路包括被配置为检测第一和第二输出条件的第一检测电路，所述控制电路被配置当检测到第一输出条件时响应于控制信号在开关控制中操作第一开关装置，并且当检测到第二输出条件时将第一开关装置操作在线性控制区域中。

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