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1. 发明授权

US6128026A Double buffered graphics and video accelerator having a write blocking memory interface and method of doing the same 失效
标题翻译：具有写阻塞存储器接口的双缓冲图形和视频加速器以及执行相同的方法
公开(公告)号：US6128026A
公开(公告)日：2000-10-03
申请号：US122422
申请日：1998-07-24
申请人： John W. Brothers, III
发明人： John W. Brothers, III
IPC分类号： G06T1/60 , G06F13/18 , G09G1/16 , G09G5/00 , G09G5/393 , G09G5/397 , G09G5/399 , G06F13/00
CPC分类号： G09G3/003 , G09G5/393 , G09G5/399 , G09G2340/02 , G09G5/001
摘要： A write blocking accelerator provides maximum concurrency between a central processing unit (CPU) and the accelerator by allowing writes to the front buffer of a dual-buffered system. The CPU issues a series of drawing commands followed by a "page flip" command. When a command parser within the accelerator receives a page flip command, it notifies a screen refresh unit reading from the front buffer that the command was received. The screen refresh unit signals a memory interface unit (MIU) to enter a write blocking mode and provides the address of the current line in the front buffer from which the screen refresh unit is reading, and the address of the last line in the front buffer. The MIU blocks all writes from drawing engines that fall into the range defined between the two addresses. The screen refresh sends updated front buffer addresses to the MIU as display data is read out of the front buffer. Accordingly, the blocked address range constantly shrinks until all writes are allowed by the MIU. At that point, the screen refresh unit signals the MIU that it has reached vertical retrace and the MIU exits write blocking mode.
摘要翻译：写阻塞加速器通过允许写入双缓冲系统的前缓冲区，在中央处理器（CPU）和加速器之间提供最大的并发性。 CPU发出一系列绘图命令，后跟“翻页”命令。当加速器内的命令解析器接收到页面翻转命令时，它通知屏幕刷新单元从前缓冲器读取该命令。屏幕刷新单元向存储器接口单元（MIU）发出信号以进入写入阻塞模式，并提供当前行在当前行中的屏幕刷新单元正在读取的地址，以及前面缓冲区中最后一行的地址。 MIU阻止来自绘图引擎的所有写入落入两个地址之间定义的范围内。屏幕刷新将更新的前缓冲区地址发送到MIU，因为显示数据从前缓冲区中读出。因此，阻塞的地址范围不断缩小，直到MIU允许所有写入。此时，屏幕刷新单元向MIU发出信号已经达到垂直回扫并且MIU退出写入阻塞模式。

2. 发明授权

US06028613A Method and apparatus for programming a graphics subsystem register set 失效
标题翻译：用于编程图形子系统寄存器集的方法和装置
公开(公告)号：US06028613A
公开(公告)日：2000-02-22
申请号：US821125
申请日：1997-03-20
申请人： Michael Larson
发明人： Michael Larson
IPC分类号： G06F9/345 , G06F9/38 , G06T1/20 , G06F15/00
CPC分类号： G06T1/20 , G06F9/345 , G06F9/3879
摘要： A graphics system includes a graphics processor for rendering graphics primitives with a display list. A host processor generates a display list which includes a command format for loading the display list into a register file. The graphics processor includes logic to encode and decode the command register to sequentially load the display list into the register file without a physical reference to the register being loaded. The command register may also be programmed to allow the graphics processor to randomly load the register file thereby shortening the processing of the display list and allowing the display list to be written during a burst cycle mode of bus operation.
摘要翻译：图形系统包括用于使用显示列表来渲染图形基元的图形处理器。主机处理器生成显示列表，其包括用于将显示列表加载到寄存器文件中的命令格式。图形处理器包括用于编码和解码命令寄存器的逻辑，以将显示列表顺序地加载到寄存器文件中，而不对正在加载的寄存器进行物理引用。命令寄存器也可以被编程为允许图形处理器随机加载寄存器文件，从而缩短显示列表的处理，并允许在总线操作的突发周期模式期间写入显示列表。

3. 发明授权

US6008794A Flat-panel display controller with improved dithering and frame rate control 失效
标题翻译：平板显示控制器，具有改进的抖动和帧速率控制
公开(公告)号：US6008794A
公开(公告)日：1999-12-28
申请号：US21718
申请日：1998-02-10
申请人： Takatoshi Ishii
发明人： Takatoshi Ishii
IPC分类号： G09G3/20 , G09G3/36 , G09G5/02
CPC分类号： G09G5/02 , G09G3/3611 , G09G3/2007 , G09G3/2018 , G09G3/2051
摘要： A flat-panel display controller generates signals to cause display of images on TFT and STN type flat-panel displays. The display controller includes dither logic and frame rate control logic. The dither logic performs dynamic and distributed dithering on pixel data to generate smooth 16 gray-shade images on the display. The dynamic and distributed dithering capabilities are programmable. Dynamic dithering is programmable to specify, two-phase, four-phase or eight-phase mixes.to generate signals for use by TFT and STN type flat-panel displays. The frame rate control logic is responsive to the dither logic and performs frame rate control on the dithered signals using stored values indicative of average pixel luminescence to generate 256 gray-shades.
摘要翻译：平板显示控制器产生信号，以便在TFT和STN型平板显示器上显示图像。显示控制器包括抖动逻辑和帧速率控制逻辑。抖动逻辑在像素数据上执行动态和分布式抖动，以在显示器上生成平滑的16灰度阴影图像。动态和分布式抖动功能是可编程的。动态抖动是可编程的，用于指定两相，四相或八相混合，以产生TFT和STN型平板显示器使用的信号。帧速率控制逻辑响应抖动逻辑并使用指示平均像素发光的存储值来对抖动信号执行帧速率控制以产生256个灰度。

4. 发明授权

US6005546A Hardware assist for YUV data format conversion to software MPEG decoder 失效
公开(公告)号：US6005546A
公开(公告)日：1999-12-21
申请号：US619203
申请日：1996-03-21
申请人： David Keene
发明人： David Keene
IPC分类号： H04N11/04 , G06F3/14 , G06T9/00 , G09G5/02 , G09G5/393 , G09G5/04
CPC分类号： G09G5/393 , G06F3/14 , G06T9/007 , G09G5/02
摘要： A display controller assists a host processor in decoding MPEG data. The display controller receives YUV data in non-pixel video format from a host CPU and perform the otherwise CPU intensive task of rasterization within the display controller. In addition, the display controller may use its internal BITBLIT engine to copy U and V data from one line in a BITBLIT operation to adjacent lines, so as to replicate U and V data. A byte mask preserves Y data on the adjacent lines from being overwritten. At the end of the BITBLIT operation, the display controller generates a signal indicating that the frame buffer has been filled with new data, and thus display controller automatically switches to reading from the newly written frame buffer.

5. 发明授权

US5958038A Computer processor with two addressable memories and two stream registers and method of data streaming of ALU operation 失效
标题翻译：具有两个可寻址存储器和两个流寄存器的计算机处理器和ALU操作的数据流传输方法
公开(公告)号：US5958038A
公开(公告)日：1999-09-28
申请号：US966904
申请日：1997-11-07
申请人： Nitin Agrawal , Sunil Nanda
发明人： Nitin Agrawal , Sunil Nanda
IPC分类号： G06F7/00 , G06F9/30 , G06F9/302 , G06F9/345 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3001 , G06F9/3013 , G06F9/345 , G06F9/3885
摘要： A processor having a modified Harvard architecture having first and second memories, an address register file divided into first and second sets of registers, first and second stream registers, and a general purpose register file for performing data streaming. The first and second sets of registers respectively address the first and second memories which, in turn, load data into the first and second stream registers. An arithmetic logic unit (ALU) accepts the stream registers and general purpose registers as inputs. Stream instructions are encoded such that a single instruction specifies an ALU operation performed on selected ALU inputs and where to store the results of the ALU operation, loads new values into the stream registers, and updates the address registers. A stream instruction has three operand fields respectively specifying two operands for the next ALU operation and a location to store the result of the current ALU operation. The bits in the fields for specifying a stream register and addressing mode are positionally overlapped with the bits for specifying a particular general purpose register. This encoding allows a simple instruction decoding mechanism while enabling parallel memory accesses and address update in a compact instruction.
摘要翻译：具有经修改的哈佛架构的处理器具有第一和第二存储器，被分成第一和第二组寄存器的地址寄存器文件，第一和第二流寄存器以及用于执行数据流的通用寄存器文件。第一和第二组寄存器分别对第一和第二存储器进行寻址，其又将数据加载到第一和第二流寄存器中。算术逻辑单元（ALU）接受流寄存器和通用寄存器作为输入。流指令被编码，使得单个指令指定对所选ALU输入执行的ALU操作以及在哪里存储ALU操作的结果，将新值加载到流寄存器中，并更新地址寄存器。流指令具有三个操作数字段，分别指定下一个ALU操作的两个操作数和存储当前ALU操作结果的位置。用于指定流寄存器和寻址模式的字段中的位与用于指定特定通用寄存器的位位置地重叠。该编码允许简单的指令解码机制，同时在紧凑指令中实现并行存储器访问和地址更新。

6. 发明授权

US5956431A System and method for fixed-rate block-based image compression with inferred pixel values 失效
标题翻译：用于推断像素值的固定速率块图像压缩的系统和方法
公开(公告)号：US5956431A
公开(公告)日：1999-09-21
申请号：US942860
申请日：1997-10-02
申请人： Konstantine I. Iourcha , Krishna S. Nayak , Zhou Hong
发明人： Konstantine I. Iourcha , Krishna S. Nayak , Zhou Hong
IPC分类号： H04N7/30 , G06T9/00 , H03M7/30 , H04N1/41 , G06K9/36
CPC分类号： H03M7/30 , G06T9/00 , G06T9/005 , H04N19/13 , H04N19/60 , H04N19/91
摘要： An image processing system includes an image encoder system and a image decoder system that are coupled together. The image encoder system includes a block decomposer and a block encoder that are coupled together. The block encoder includes a color quantizer and a bitmap construction module. The block decomposer breaks an original image into blocks. Each block is then processed by the block encoder. Specifically, the color quantizer selects some number of base points, or codewords, that serve as reference pixel values, such as colors, from which quantized pixel values are derived. The bitmap construction module then maps each pixel colors to one of the derived quantized colors. The codewords and bitmap are output as encoded image blocks. The decoder system includes a block decoder. The block decoder includes a block type detector, one or more decoder units, and an output selector. Using the codewords of the encoded data blocks, the comparator and the decoder units determine the quantized colors for the encoded image block and map each pixel to one of the quantized colors. The output selector outputs the appropriate color, which is ordered in an image composer with the other decoded blocks to output an image representative of the original image. A method for encoding an original image and for decoding the encoded image to generate a representation of the original image is also disclosed.
摘要翻译：图像处理系统包括耦合在一起的图像编码器系统和图像解码器系统。图像编码器系统包括耦合在一起的块分解器和块编码器。块编码器包括颜色量化器和位图构造模块。块分解器将原始图像分割成块。然后由块编码器处理每个块。具体地说，色彩量化器选择一些数量的基点或码字，其作为从其导出量子化像素值的参考像素值，例如颜色。然后，位图构造模块将每个像素颜色映射到衍生的量化颜色之一。码字和位图作为编码图像块输出。解码器系统包括块解码器。块解码器包括块类型检测器，一个或多个解码器单元和输出选择器。使用编码数据块的码字，比较器和解码器单元确定编码图像块的量化颜色，并将每个像素映射到量化颜色之一。输出选择器输出适当的颜色，其在图像编辑器中与其他解码块排序，以输出代表原始图像的图像。还公开了一种用于对原始图像进行编码和解码编码图像以生成原始图像的表示的方法。

7. 发明授权

US5903180A Voltage tolerant bus hold latch 失效
标题翻译：耐压母线保持闩锁
公开(公告)号：US5903180A
公开(公告)日：1999-05-11
申请号：US900084
申请日：1997-07-24
申请人： Yuwen Hsia , Sarathy Sribhashyam
发明人： Yuwen Hsia , Sarathy Sribhashyam
IPC分类号： H01L27/00 , H03K20060101 , H03L5/00
CPC分类号： H03K3/356104 , H03K3/0375
摘要： A voltage tolerant bus hold latch comprises a first buffer transistor, a sense transistor, a low voltage latch, a node voltage controller and a pull-up circuit. The low voltage latch is coupled to the input by the first transistor. The node voltage controller is coupled to the input by the sense transistor. The node voltage controller has a pair of additional inputs coupled to the output of the low voltage latch. The output of the node voltage controller is coupled to control the operation of the pull-up circuit. The pull-up circuit is coupled to the supply voltage for the lower voltage circuitry, and has another control input coupled to the output of the low voltage latch. The output of the pull-up circuit is coupled to the input of the voltage tolerant latch. The pull-up circuit is selectively activated to pull the input of the latch to a high voltage level. The node voltage controller acts as voltage divider to maintain a voltage difference across the gate-to-drain of the pull-up circuit within the operating tolerance of the pull-up circuit (Vtp+2*Vtn).
摘要翻译：电压容限总线保持锁存器包括第一缓冲晶体管，感测晶体管，低电压锁存器，节点电压控制器和上拉电路。低电压锁存器通过第一晶体管耦合到输入端。节点电压控制器通过感测晶体管耦合到输入端。节点电压控制器具有耦合到低压锁存器的输出的一对附加输入。节点电压控制器的输出被耦合以控制上拉电路的操作。上拉电路耦合到低电压电路的电源电压，并且具有耦合到低电压锁存器的输出的另一个控制输入。上拉电路的输出耦合到电压容限锁存器的输入端。选择性地激活上拉电路以将锁存器的输入拉到高电压电平。节点电压控制器用作分压器，以在上拉电路的工作容差（Vtp + 2 * Vtn）内保持上拉电路的栅极到漏极之间的电压差。

8. 发明授权

US5889499A System and method for the mixing of graphics and video signals 失效
标题翻译：用于混合图形和视频信号的系统和方法
公开(公告)号：US5889499A
公开(公告)日：1999-03-30
申请号：US683102
申请日：1996-07-16
申请人： Robert Marshall Nally , Christopher Lloyd Reinert
发明人： Robert Marshall Nally , Christopher Lloyd Reinert
IPC分类号： G09G5/02 , G09G5/395 , G09G5/00
CPC分类号： G09G5/395 , G09G2340/125 , G09G5/02
摘要： Disclosed is a system and method for mixing a plurality of graphics and video signals to create a desired output format, the desired output format being a mixture of the received signals. The mechanisim for achieving this rich format is a multi-modal graphics video overlay controller. The controller having a set of opcodes, selects a subset of the opcode set, this selection being a function of a desired output format of the mixed signals. The subset of opcodes is then utilized to control the means for selectively switching among the received graphics and video signals to create the desired output format. The selective switching is accomplished on a pixel by pixel basis.
摘要翻译：公开了一种用于混合多个图形和视频信号以产生期望的输出格式的系统和方法，期望的输出格式是接收信号的混合。实现这种丰富格式的机制是多模式图形视频覆盖控制器。控制器具有一组操作码，选择操作码集合的子集，该选择是混合信号的期望输出格式的函数。然后使用操作码的子集来控制用于在所接收的图形和视频信号之间选择性地切换的装置，以创建期望的输出格式。选择性切换是以逐个像素为基础完成的。

9. 发明授权

US5826074A Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register 失效
标题翻译： 32位架构的扩展，用于具有共享超页寄存器的64位寻址
公开(公告)号：US5826074A
公开(公告)日：1998-10-20
申请号：US755547
申请日：1996-11-22
申请人： James S. Blomgren
发明人： James S. Blomgren
IPC分类号： G06F9/38 , G06F9/32 , G06F9/42
CPC分类号： G06F9/3804 , G06F9/3861
摘要： A processor has 64-bit operand execution pipelines, but a 32-bit branch pipeline. The branch pipeline contains registers to hold the lower 32-bit sub-addresses of 64-bit target and sequential addresses for conditional branches which have been predicted but not yet resolved. A shared register contains the upper 32 address bits for the target and sequential sub-addresses. All 32-bit target and sequential sub-address registers in the branch pipeline share the single 32-bit shared register holding the upper 32 address bits. The branch pipeline can only process instructions with the same upper 32 address bits, which define a 4 Giga-Byte super-page. When an instruction references an address in a different 4 Giga-Byte super-page, then the branch pipeline stalls until all other branch instructions have completed. The new super-page's upper 32 address bits are then loaded into the shared register. A super-page crossing is detected by a carry out of bit 32 in the 32-bit target or sequential address adders. Branches crossing to a new super-page are always predicted as taken. The super-page address is incremented during mis-prediction recovery when the sequential instruction stream crosses to a new super-page.
摘要翻译：一个处理器有64位操作数执行流水线，但是一个32位分支流水线。分支流水线包含寄存器，用于保存已经预测但尚未解决的条件分支的64位目标和顺序地址的低32位子地址。共享寄存器包含目标和顺序子地址的高32位地址位。分支流水线中的所有32位目标和顺序子地址寄存器共享保存高32位地址位的单个32位共享寄存器。分支流水线只能处理具有相同的高32位地址位的指令，它们定义了4千兆字节超级页面。当指令引用不同的4 Giga-Byte超级页面中的地址时，分支流水线将停止，直到所有其他分支指令完成。新的超级页面的高32位地址位被加载到共享寄存器中。通过32位目标或顺序地址加法器中的位32的进位检测超级页面交叉。跨越一个新的超级页面的分支总是被预测为采取。当顺序指令流跨越到新的超级页面时，超页面地址在错误预测恢复期间增加。

10. 发明授权

US5777590A Grayscale shading for liquid crystal display panels 失效
标题翻译：液晶显示面板的灰度阴影
公开(公告)号：US5777590A
公开(公告)日：1998-07-07
申请号：US519690
申请日：1995-08-25
申请人： Nirmal R. Saxena , Sridhar Manthani
发明人： Nirmal R. Saxena , Sridhar Manthani
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G06T5/10
CPC分类号： G09G3/3611 , G09G3/2018 , G09G3/2051
摘要： An LCD controller for use e.g. in a portable computer provides gray scale shading for both monochromatic and color displays using frame rate control modulation for intensity shading for each pixel. The gray scale shading process and circuit do not require any memory for storing phase tiling matrices or frame modulation pattern sequences; both of these instead are generated in real time using a linear matrix logic structure. Use of linear matrix operations also allows generation of various phase shifts of frame modulation pattern sequences to provide a better image on the display. In addition to providing programmable 4, 8, or 16 intensity levels, the present method and apparatus provide that vertically, horizontally or diagonally adjacent pixels on the display never have the same phase in the same frame, and in addition that the pixel display drivers are uniformly loaded.
摘要翻译： LCD控制器。在便携式计算机中，使用针对每个像素的强度阴影的帧速率控制调制来为单色和彩色显示器提供灰度阴影。灰度阴影处理和电路不需要用于存储相位矩阵或帧调制图案序列的任何存储器; 这两者都是使用线性矩阵逻辑结构实时生成的。使用线性矩阵运算还允许生成帧调制图案序列的各种相移以在显示器上提供更好的图像。除了提供可编程的4,8或16个强度级别之外，本方法和装置提供了显示器上的垂直，水平或对角相邻的像素在相同的帧中从不具有相同的相位，而且像素显示驱动器均匀加载

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