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1. 发明授权

US08859392B1 Manufacturing method of power semiconductor 有权
标题翻译：功率半导体制造方法
公开(公告)号：US08859392B1
公开(公告)日：2014-10-14
申请号：US13974142
申请日：2013-08-23
申请人： Mosel Vitelic Inc.
发明人： Chien-Ping Chang
IPC分类号： H01L21/30 , H01L23/10 , H01L29/66
CPC分类号： H01L29/66348 , H01L21/187 , H01L21/6835 , H01L2221/68327 , H01L2221/6834
摘要： A manufacturing method of a power semiconductor includes steps of providing a first semiconductor substrate and a second semiconductor substrate, forming a metal oxide semiconductor layer on a first surface of the first semiconductor substrate, grinding a second surface of the first semiconductor substrate, forming a N-type buffer layer and a P-type injection layer on a third surface of the second semiconductor substrate through ion implanting, grinding a fourth surface of the second semiconductor substrate, and combining the second surface of the first semiconductor substrate with the third surface of the second semiconductor substrate for forming a third semiconductor substrate. As a result, the present invention achieves the advantages of enhancing the process flexibility and un-limiting the characteristics of the power semiconductor.
摘要翻译：功率半导体的制造方法包括以下步骤：提供第一半导体衬底和第二半导体衬底，在第一半导体衬底的第一表面上形成金属氧化物半导体层，研磨第一半导体衬底的第二表面，形成N 型缓冲层和P型注入层，通过离子注入在第二半导体衬底的第三表面上，研磨第二半导体衬底的第四表面，并将第一半导体衬底的第二表面与用于形成第三半导体衬底的第二半导体衬底。结果，本发明实现了提高工艺灵活性和不限制功率半导体的特性的优点。

2. 发明授权

US07888160B2 Process of manufacturing solar cell 有权
标题翻译：太阳能电池制造工艺
公开(公告)号：US07888160B2
公开(公告)日：2011-02-15
申请号：US12314468
申请日：2008-12-11
申请人： Chang Hong Shen , Pei Ting Lo
发明人： Chang Hong Shen , Pei Ting Lo
IPC分类号： H01L21/00
CPC分类号： H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A process of manufacturing a solar cell is disclosed. The process comprises steps of (a) providing a semiconductor substrate, (b) forming a dielectric layer with amorphous silicon structure on the semiconductor substrate, (c) partially removing the dielectric layer with amorphous silicon structure to expose parts of the semiconductor substrate, (d) simultaneously forming a heavily doped region on a surface of the exposed semiconductor substrate and a lightly doped region on a surface of the unexposed semiconductor substrate using the dielectric layer with amorphous silicon structure as a translucent barrier layer, (e) removing the dielectric layer with amorphous silicon structure, (f) forming an anti-reflection coating on the semiconductor substrate, and (g) forming a first electrode on the anti-reflection coating and coupled with the heavily doped region.
摘要翻译：公开了一种制造太阳能电池的方法。该方法包括以下步骤：（a）提供半导体衬底，（b）在半导体衬底上形成具有非晶硅结构的电介质层，（c）用非晶硅结构部分去除电介质层以暴露半导体衬底的部分（ d）使用具有非晶硅结构的电介质层作为透光性阻挡层，在暴露的半导体衬底的表面上同时形成重掺杂区域和未曝光半导体衬底的表面上的轻掺杂区域，（e）去除介电层（f）在半导体衬底上形成抗反射涂层，和（g）在抗反射涂层上形成第一电极并与重掺杂区域耦合。

3. 发明申请

US20080280430A1 METHOD OF FORMING FILMS IN A TRENCH 审中-公开
标题翻译：在TRENCH中形成膜的方法
公开(公告)号：US20080280430A1
公开(公告)日：2008-11-13
申请号：US12120885
申请日：2008-05-15
申请人： Shih-Chi Lai , Tun-Fu Hung , Yi-Fu Chung , Jen-Chieh Chang
发明人： Shih-Chi Lai , Tun-Fu Hung , Yi-Fu Chung , Jen-Chieh Chang
IPC分类号： H01L21/283
CPC分类号： H01L29/513 , H01L21/31053 , H01L21/31662 , H01L21/3185 , H01L29/66734
摘要： A method of forming films in a trench is applied to the manufacturing process of a power MOS device. In one embodiment, the method comprises providing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a first dielectric layer on sidewalls of the trench, forming a second dielectric layer on the first dielectric layer, and forming a polysilicon layer in the trench. The method of forming films in a trench of the present invention can reduce or eliminate the thermal stress resulting from the different thermal expansion coefficients of different material layers after high temperature process.
摘要翻译：在沟槽中形成膜的方法被应用于功率MOS器件的制造过程。在一个实施例中，该方法包括提供半导体衬底，在半导体衬底中形成沟槽，在沟槽的侧壁上形成第一电介质层，在第一电介质层上形成第二电介质层，以及在沟槽中形成多晶硅层。在本发明的沟槽中形成膜的方法可以降低或消除由高温处理后的不同材料层的不同热膨胀系数产生的热应力。

4. 发明授权

US07205196B2 Manufacturing process and structure of integrated circuit 有权
标题翻译：集成电路的制造工艺和结构
公开(公告)号：US07205196B2
公开(公告)日：2007-04-17
申请号：US11035700
申请日：2005-01-14
申请人： Hsin-Huang Hsieh , Chien-Ping Chang , Mao-Song Tseng , Tien-Min Yuan
发明人： Hsin-Huang Hsieh , Chien-Ping Chang , Mao-Song Tseng , Tien-Min Yuan
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/823437 , H01L27/0266 , H01L27/0883 , H01L29/66734 , H01L29/7803 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device simultaneously. The present invention not only has overcome the problem of the electric leakage, but also has the advantages of withstanding a higher voltage, reducing the relevant cost and increasing the yields. The present invention possesses the outstanding technical features in the field of the power device.
摘要翻译：本发明提供一种集成电路的制造工艺和结构。在一个实施例中，使用一个多晶硅层沉积和一个多晶硅层蚀刻来同时形成沟槽器件的栅极和平面器件的多晶硅层。本发明不仅克服了漏电问题，而且具有耐高压，降低相关成本，提高产量的优点。本发明在功率器件领域具有突出的技术特点。

5. 发明授权

US07192789B2 Method for monitoring an ion implanter 有权
标题翻译：监测离子注入机的方法
公开(公告)号：US07192789B2
公开(公告)日：2007-03-20
申请号：US10942381
申请日：2004-09-15
申请人： Chun Te Lin , Chih Sheng Yang , Hong Zhi Lee , Ta-Te Chen
发明人： Chun Te Lin , Chih Sheng Yang , Hong Zhi Lee , Ta-Te Chen
IPC分类号： H01L21/00 , H01L21/425 , G01R31/26
CPC分类号： H01L22/34
摘要： A method for monitoring an ion implanter is disclosed. In one embodiment, the method comprises providing a wafer, forming a barrier layer on the surface of the wafer wherein the barrier layer has a substantial blocking effect on ion implantation, performing an ion implantation process to the wafer, performing a thermal treatment process, removing the barrier layer, and measuring a physical property of the wafer. The measured physical property of the wafer can be used to ascertain the status of the ion implanter. For instance, the measured physical property can be used to determine whether the ion implanter has problems when the energy or concentration of the implanted ions is changed.
摘要翻译：公开了一种监测离子注入机的方法。在一个实施例中，该方法包括提供晶片，在晶片的表面上形成阻挡层，其中阻挡层对离子注入具有显着的阻塞作用，对晶片执行离子注入工艺，执行热处理工艺，去除阻挡层，并测量晶片的物理性质。可以使用测量的晶片的物理特性来确定离子注入机的状态。例如，当注入的离子的能量或浓度改变时，测量的物理性质可用于确定离子注入机是否存在问题。

6. 发明授权

US07126853B2 Electronic memory having impedance-matched sensing 有权
标题翻译：具有阻抗匹配感测的电子存储器
公开(公告)号：US07126853B2
公开(公告)日：2006-10-24
申请号：US10640929
申请日：2003-08-14
申请人： Jongjun Kim
发明人： Jongjun Kim
IPC分类号： G11C16/04
CPC分类号： G11C7/06 , G11C7/14 , G11C7/18 , G11C16/28
摘要： An electronic memory, typically a flash EPROM, contains an array of memory sections (40), each containing an array of memory cells (54). Global bit lines (60) fully traverse the memory. Local bit lines (58) partially traverse the memory. Data stored in the memory is sensed with an arrangement that utilizes impedance matching to achieve high sensing accuracy with low noise sensitivity. The impedance matching may be provided solely from the sections and lines of the memory or partially from a separate reference memory section (102) that contains reference memory cells (104).
摘要翻译：通常为闪存EPROM的电子存储器包含存储部分（40）的阵列，每个存储器部分包含存储器单元阵列（54）。全局位线（60）完全遍历存储器。本地位线（58）部分地遍历存储器。使用利用阻抗匹配的装置来感测存储在存储器中的数据，以实现具有低噪声灵敏度的高感测精度。阻抗匹配可以仅从存储器的部分和线路部分提供，或部分地从包含参考存储器单元（104）的单独参考存储器部分（102）提供。

7. 发明授权

US07092836B2 Method for locating wiring swap in a hi-fix structure of a simultaneous multi-electronic device test system 有权
标题翻译：一种用于同时多电子设备测试系统的固定结构中的布线互换的方法
公开(公告)号：US07092836B2
公开(公告)日：2006-08-15
申请号：US10652954
申请日：2003-08-28
申请人： Hsiao-Chi Lou , Ween-Chen Lu
发明人： Hsiao-Chi Lou , Ween-Chen Lu
IPC分类号： G01R27/28 , G01R31/00
CPC分类号： G01R1/0416
摘要： A method for locating wiring swap in a hi-fix structure of a simultaneous multi-electronic device test system is introduced to screen the complicated wiring state of the hi-fix structure and to pinpoint the wiring swap thereinside as well. The hi-fix structure has at least S socket slots for testing electronic devices which each of the electronic devices has at least R leads. The present method, firstly, is to prepare R test unit sets which each of the test unit set includes S identical lead-off elements. Then, all R test unit sets are tested, in order, on the hi-fix structure and the respective test results are recorded. Finally, by analyzing the test results, the wiring swap inside the hi-fix structure can be accurately located.
摘要翻译：引入同时多电子装置测试系统的高固定结构中的布线互换的方法，以屏蔽高固定结构的复杂布线状态，并精确定位其内部的布线互换。高固定结构至少具有用于测试每个电子设备至少具有R引线的电子设备的S插槽。本方法首先是准备R个测试单元组，每个测试单元组包括S个相同的引出元件。然后，按照Hi-fix结构的顺序测试所有的R测试单元组，并记录相应的测试结果。最后，通过分析测试结果，可以精确定位Hi-fix结构内的接线互换。

8. 发明授权

US07087958B2 Termination structure of DMOS device 有权
标题翻译： DMOS设备终端结构
公开(公告)号：US07087958B2
公开(公告)日：2006-08-08
申请号：US10771957
申请日：2004-02-03
申请人： Chiao-Shun Chuang , Chien-Ping Chang , Mao-Song Tseng , Hsing-Huang Hsieh
发明人： Chiao-Shun Chuang , Chien-Ping Chang , Mao-Song Tseng , Hsing-Huang Hsieh
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L29/402 , H01L29/407 , H01L29/7813
摘要： In one embodiment of the invention, a semiconductor device set includes at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and includes a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer. The trench-typed termination structure has a trench profile and includes an oxide layer in the trench profile. A termination polysilicon layer with discrete features separates the termination polysilicon layer. An isolation layer covers the termination polysilicon layer and filling the discrete features. The trench-typed MOSFET and the trench-typed termination structure may be formed on a DMOS device including an N+ silicon substrate, an N epitaxial layer on the N+ silicon substrate, and a P epitaxial layer on the N epitaxial layer. The trench profiles of the trench-typed MOSFET and of the trench-typed termination structure may penetrate through the P epitaxial layer into the N epitaxial layer.
摘要翻译：在本发明的一个实施例中，半导体器件组包括至少一个沟槽型MOSFET和沟槽型端接结构。沟槽型MOSFET具有沟槽轮廓并且在沟槽轮廓中包括栅极氧化物层，并且在栅极氧化物层上包括多晶硅层。沟槽式端接结构具有沟槽轮廓并且在沟槽轮廓中包括氧化物层。具有离散特征的端接多晶硅层分离端接多晶硅层。隔离层覆盖终端多晶硅层并填充离散特征。沟槽型MOSFET和沟槽型端接结构可以形成在包括N +硅衬底，N +硅衬底上的N外延层和N外延层上的P外延层的DMOS器件上。沟槽型MOSFET和沟槽型端接结构的沟槽轮廓可以穿透P外延层进入N外延层。

9. 发明授权

US07070484B2 Pad break-in method for chemical mechanical polishing tool which polishes with ceria-based slurry 有权
标题翻译：用二氧化铈浆料抛光的化学机械抛光工具的垫片插入方法
公开(公告)号：US07070484B2
公开(公告)日：2006-07-04
申请号：US10851549
申请日：2004-05-21
申请人： Kuo-Chun Wu , Wee-chen Richard Gan , Karen Wong
发明人： Kuo-Chun Wu , Wee-chen Richard Gan , Karen Wong
IPC分类号： B24B1/00
CPC分类号： B24B53/017 , B24B37/042
摘要： A chemical mechanical polishing (CMP) method is disclosed in which a new polishing pad is broken-in and conditioned into a steady operating state while using a silica (SiO2) based CMP slurry and where the broken-in and conditioned pad is afterwards used for polishing patterned workpieces (e.g., semiconductor wafers) with a ceria (CeO2) based CMP slurry. The approach shortens break-in time and appears to eliminate a first wafer effect usually seen following break-in with ceria-based CMP slurries.
摘要翻译：公开了一种化学机械抛光（CMP）方法，其中在使用基于二氧化硅（SiO 2/2））的CMP浆料的同时，将新的抛光垫破碎并调节至稳定的运行状态，然后将调节垫用于用基于二氧化铈（CeO 2 N 2）的CMP浆料抛光图案化工件（例如，半导体晶片）。该方法缩短了插入时间，并且似乎消除了通过二氧化铈基CMP浆料破裂后通常看到的第一晶片效应。

10. 发明授权

US07040958B2 Torque-based end point detection methods for chemical mechanical polishing tool which uses ceria-based CMP slurry to polish to protective pad layer 有权
标题翻译：用于化学机械抛光工具的基于扭矩的终点检测方法，其使用二氧化铈基CMP浆料抛光至保护垫层
公开(公告)号：US07040958B2
公开(公告)日：2006-05-09
申请号：US10851378
申请日：2004-05-21
申请人： Wee-chen Richard Gan , Karen Wong , Kuo-Chun Wu
发明人： Wee-chen Richard Gan , Karen Wong , Kuo-Chun Wu
IPC分类号： B24B49/00
CPC分类号： B24B37/013 , B24B49/16
摘要： A chemical mechanical polishing (CMP) method is disclosed in which a torque-based end-point algorithm is used to determine when polishing should be stopped. The end-point algorithm is applicable to situations where a ceria (CeO2) based CMP slurry is used for further polishing, pre-patterned and pre-polished workpieces (e.g., semiconductor wafers) which have a high friction over-layer (e.g., HDP-oxide) and a comparatively, lower friction and underlying layer of sacrificial pads (e.g., silicon nitride pads). A mass production wise, reliable and consistent signature point in the friction versus time waveform of a torque-representing signal is found and used to trigger an empirically specified duration of overpolish. A database may be used to define the overpolish time as a function of one or more relevant parameters.
摘要翻译：公开了一种化学机械抛光（CMP）方法，其中使用基于扭矩的端点算法来确定何时停止抛光。端点算法适用于将基于二氧化铈（CeO 2/2）的CMP浆料用于进一步抛光，预图案化和预抛光工件（例如，半导体晶片）的情况，其具有高的摩擦过度层（例如，HDP氧化物）和相对较低的摩擦和下层的牺牲垫（例如，氮化硅垫）。发现在扭矩表示信号的摩擦时间波形中的大规模生产明智，可靠和一致的签名点，并用于触发经验规定的过度推测的持续时间。可以使用数据库来定义作为一个或多个相关参数的函数的过时时间。

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