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1. 发明授权

US6000051A Method and apparatus for high-speed interconnect testing 失效
标题翻译：高速互连测试的方法和装置
公开(公告)号：US6000051A
公开(公告)日：1999-12-07
申请号：US948842
申请日：1997-10-10
申请人： Benoit Nadeau-Dostie , Jean-Francois Cote
发明人： Benoit Nadeau-Dostie , Jean-Francois Cote
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/31855
摘要： A method of testing high speed interconnectivity of circuit boards having components operable at a high speed system clock, employing an IEEE 1149.1 standard test method in which test data is shifted into and from the components at the rate of a test clock during Shift.sub.-- In and Shift.sub.-- Out operations, and having an Update operation and a Capture operation between the Shift.sub.-- In and Shift.sub.-- Out operations, the components including a first group of components capable of performing the Update and Capture operations at the rate of the Test Clock only and a second group of components capable of performing the Update and Capture operations at the rate of the system clock, the method comprising the steps of performing the Shift.sub.-- In operation in all of the components concurrently at the rate of the Test Clock; performing the Update and Capture Operations in the first group of components at the rate of the Test Clock; and performing the Update and Capture Operations in the second group of components at the rate of the system Clock. The method employs a novel integrated circuit, test controller and boundary scan cells.
摘要翻译：一种测试具有可在高速系统时钟操作的部件的电路板的高速互连性的方法，采用IEEE 1149.1标准测试方法，其中测试数据在Shift-In期间以测试时钟的速率被移入和移出部件， Shift-Out操作，并且在Shift-In和Shift-Out操作之间具有Update操作和Capture操作，这些组件包括能够以仅测试时钟的速率执行Update和Capture操作的第一组组件，以及能够以系统时钟的速率执行更新和捕获操作的第二组组件，所述方法包括以所述测试时钟的速率同时在所有组件中执行所述移位操作的步骤; 以测试时钟的速率在第一组组件中执行更新和捕获操作; 并以系统时钟的速率在第二组组件中执行更新和捕获操作。该方法采用新颖的集成电路，测试控制器和边界扫描单元。

2. 发明授权

US5812469A Method and apparatus for testing multi-port memory 失效
标题翻译：用于测试多端口存储器的方法和装置
公开(公告)号：US5812469A
公开(公告)日：1998-09-22
申请号：US775856
申请日：1996-12-31
申请人： Benoit Nadeau-Dostie , Jean-Francois Cote
发明人： Benoit Nadeau-Dostie , Jean-Francois Cote
IPC分类号： G11C8/16 , G11C29/28 , G11C7/00
CPC分类号： G11C29/28 , G11C8/16
摘要： A method of and apparatus for testing multi-port memory performs a shadow read to an adjacent memory cell concurrent with a write operation associated with typical read-write testing. In the presence of a bit wire short or a word wire short, the concurrent read of an adjacent memory cell will cause the value of that cell to be corrupted. The corrupted value is then found by the read-write testing. Consequently, the testing takes no longer than read-write testing. In addition, the testing scheme can be modified for memory with read only ports. An embodiment of the apparatus employs an exclusive OR gate on the least significant bit of the test row address line to generate the shadow read address.
摘要翻译：用于测试多端口存储器的方法和装置对与典型读写测试相关联的写操作同时执行对相邻存储器单元的影子读取。在有线短路或字线短路的情况下，相邻存储单元的并发读取将导致该单元的值被破坏。然后通过读写测试发现损坏的值。因此，测试不再需要读写测试。此外，可以使用只读端口对存储器修改测试方案。该装置的实施例在测试行地址线的最低有效位上采用异或门来产生影子读取地址。

3. 发明授权

US5923676A Bist architecture for measurement of integrated circuit delays 失效
标题翻译：用于测量集成电路延迟的Bist架构
公开(公告)号：US5923676A
公开(公告)日：1999-07-13
申请号：US771302
申请日：1996-12-20
申请人： Stephen K. Sunter , Benoit Nadeau-Dostie
发明人： Stephen K. Sunter , Benoit Nadeau-Dostie
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/31858
摘要： A built-in self-test (BIST) method and apparatus for digital integrated circuits (ICs) and for systems including multiple ICs, measures signal propagation delays in combinational and sequential logic, set-up and hold times, and tri-state enable/disable times, from any circuit node to any other circuit node including pin-to-pin and from one IC to another. The IC under test is provided with two test bus conductors passing near every circuit node of interest and connected thereto by switches or buffers. During test, an oscillator is created including the test bus, a constant delay, counters, and a delay path of interest or a reference path. The delay path of interest may include e.g. an analog filter. The oscillation period of the oscillator when the reference path is selected is subtracted from the oscillation period when the oscillator includes a delay path of interest. A circuit automatically accommodates inverting and non-inverting paths. A delay copier copies the delay between any two signal events, without injecting any test signal into the circuit under test (e.g. on-line test), and the delay copy can be measured by selecting it in the oscillator.
摘要翻译：用于数字集成电路（IC）和包括多个IC的系统的内置自测（BIST）方法和装置，测量组合和顺序逻辑中的信号传播延迟，建立和保持时间，以及三态使能/ 禁止时间，从任何电路节点到包括引脚到引脚和从一个IC到另一个的任何其他电路节点。被测试的IC设有两个测试总线导体，通过靠近感兴趣的每个电路节点并通过开关或缓冲器与其连接。在测试期间，创建振荡器，包括测试总线，恒定延迟，计数器和感兴趣的延迟路径或参考路径。感兴趣的延迟路径可以包括例如模拟滤波器。当振荡器包括感兴趣的延迟路径时，从振荡周期中减去当选择参考路径时振荡器的振荡周期。电路自动适应反相和非反相路径。延迟复印机复制任何两个信号事件之间的延迟，而不将任何测试信号注入被测电路（例如在线测试），并且延迟复制可以通过在振荡器中选择来测量。

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