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    • 3. 发明申请
    • Projection system
    • 投影系统
    • US20060097958A1
    • 2006-05-11
    • US10521257
    • 2003-07-11
    • Holger Monch
    • Holger Monch
    • G02F1/00
    • H04N9/3114H04N9/3155H04N9/3194
    • A projection system having a projection display (20), at least one light source (10), and a sensor means for sensing and compensating for changes in the luminous flux emitted by the at least one light source (10) is described. The sensor means comprises in this case at least one sensor arrangement (30; 31, 32; 33, 34) for sensing components (M) of the light from the light source (10) that are directed into a region surrounding an entering face of an optical component (11) of the projection system. It has been found that there is a very good correlation between these components (M) of the light from the light source (10) and those other components (1) of the light that actually reach the projection display (20), which means that by controlling a power supply unit (10c) for the light source (10) and/or a driver unit (20a) driving the projection display (20) in a suitable manner it is possible very effectively to suppress fluctuations in brightness that occur as a result of, for example, unstable arc discharges.
    • 描述了具有投影显示器(20),至少一个光源(10)和用于感测和补偿由至少一个光源(10)发射的光束变化的传感器装置的投影系统。 传感器装置在这种情况下包括至少一个用于感测来自光源(10)的光的部件(M)的传感器装置(30; 31,32,33,34),该传感器装置被引导到围绕进入面的区域 投影系统的光学部件(11)。 已经发现,来自光源(10)的光的这些分量(M)和实际到达投影显示器(20)的光的那些其它分量(1)的这些分量(M)之间存在非常好的相关性,这意味着 通过以合适的方式控制用于光源(10)和/或驱动投影显示器(20)的驱动器单元(20a)的电源单元(10c),可以非常有效地抑制发生的亮度波动 作为例如不稳定的电弧放电的结果。
    • 5. 发明申请
    • Plasma display panel electrode and phosphor structure
    • 等离子显示面板电极和荧光粉结构
    • US20050151704A1
    • 2005-07-14
    • US10507677
    • 2003-03-17
    • Bart SaltersSiebe De Zwart
    • Bart SaltersSiebe De Zwart
    • G09G3/20G09G3/293G09G3/298H01J11/12H01J11/32G09G3/28
    • H01J11/32G09G3/2003G09G3/2022G09G3/293G09G3/298G09G2300/0452G09G2310/0218H01J11/12H01J2211/265H01J2211/326H01J2211/365
    • The invention relates to an AC plasma display panel (12) of the surface discharge type, and more specifically to the structure of the address electrodes (5) of the panel and of the phosphor elements, and to a plasma display panel device comprising such a panel. According to the invention, only one address electrode (5) is used for one out of every two columns. Scan electrodes (8) and common electrodes (7) may comprise transparent parts (11). These parts (11) may extend over one out every two cells in a checkerboard fashion. In a preferred embodiment, the columns may have alternating wide (15) and narrow (16) cells (2). Furthermore, each cell has a neighbor-cell of the same color on the same address electrode but in a neighboring column and in a neighboring row. The display panel device comprises a driving circuit (22) arranged such that in at least one of the sub-fields the neighboring cells are addressed simultaneously.
    • 本发明涉及一种表面放电型的AC等离子体显示面板(12),更具体地说涉及面板和荧光体元件的寻址电极(5)的结构,以及包括这样的等离子体显示面板装置 面板。 根据本发明,每两列中只有一个地址电极(5)被使用。 扫描电极(8)和公共电极(7)可以包括透明部分(11)。 这些部件(11)可以以棋盘方式每两个单元延伸一个。 在优选实施例中,柱可以具有交替的宽(15)和窄(16)单元(2)。 此外,每个单元在相同地址电极上具有相同颜色的相邻单元,但是在相邻列和相邻行中。 显示面板装置包括驱动电路(22),其布置成使得在至少一个子场中相邻小区被同时寻址。
    • 6. 发明申请
    • Programmable delay indexed data path register file for array processing
    • 用于阵列处理的可编程延迟索引数据路径寄存器文件
    • US20030062927A1
    • 2003-04-03
    • US10026258
    • 2001-12-21
    • Koniklijke Philips Electronics N.V.
    • Krishnamurthy VaidyanathanGeoffrey Burns
    • G01R001/00
    • G06F9/30098G06F9/3013G06F9/30134
    • A delay addressed data path register file is designed for use in a programmable processor making up a cell in a multi-processor or array signal processing system. The delay addressable register file is particularly useful in, inter alia, adaptive filters where the filter update latency is variable, interpolation filters where the interpolation factor needs to be programmable, and decimation filters where the decimation factor needs to be programmable. The programmability is achieved in an efficient manner, reducing the number of cycles required to perform this task. A single parameter, the nulldelay limitnull value, is programmed at start-up, setting up an internal delay-line within the register file of the processor. Thus, any of the delayed registers can be addressed by specifying the delay index during run-time. The delay line advances one location, modulo nulldelay-limitnull, when the processing loop starts a new iteration.
    • 延迟寻址数据路径寄存器文件被设计用于构成多处理器或阵列信号处理系统中的单元的可编程处理器。 延迟寻址寄存器文件尤其适用于滤波器更新延迟可变的自适应滤波器,内插因子需要可编程的插值滤波器以及抽取因子需要被编程的抽取滤波器。 可编程性以有效的方式实现,减少执行此任务所需的周期数。 在启动时,单个参数“延迟限制”值被编程,在处理器的寄存器文件内设置内部延迟线。 因此,可以通过在运行时指定延迟指数来解决任何延迟寄存器。 当处理循环开始新的迭代时,延迟线前进一个位置,模数“延迟限制”。
    • 9. 发明申请
    • 3D video scalable video encoding method
    • 3D视频可缩放视频编码方法
    • US20070053435A1
    • 2007-03-08
    • US10574620
    • 2004-10-01
    • Ihor Kirenko
    • Ihor Kirenko
    • H04B1/66
    • H04N19/615H04N19/13H04N19/547H04N19/61H04N19/63
    • The present invention relates to a method of encoding a sequence of frames comprising the steps of dividing the sequence of frames into groups of N frames (F1-F8) with size H*W, one level sparial wavelet-based filtering (SF) the frames of a group to generate a first spatial subband (S1) of a first decomposition level comprising N low-low spatially filtered frames (LLs) with size H/2*W/2, doing motion estimation (ME1) on pairs of the low-low spatially filtered frames (LLS), resulting in a set of motion vector fields comprising N/2 fields, and motion-compensated temporal wavelet-based filtering (MCTF) the low-low spatially filtered frames (LLs) based on the set of motion vector fields, resulting in a first temporal subband (ST1) of a first decomposition level comprising N temporally filtered frames. The sequence comprising the spatial filtering step, the motion estimation step and the motion compensated filtering step is then iterated on frames having the lowest frequency in both temporal and spatial domains until one low-temporal frequency frame per temporal subband is left.
    • 本发明涉及一种编码帧序列的方法,包括以下步骤:将帧序列划分成具有大小H * W的N帧(F 1 -F 8)组,一级基于小波的滤波(SF) 生成具有大小为H / 2 * W / 2的N个低低空间滤波帧(LL)的第一分解级的第一空间子带(S1)的帧,在对上进行运动估计(ME 1) 的低低空间滤波帧(LLS),导致一组包含N / 2场的运动矢量场和基于运动补偿的基于时间小波的滤波(MCTF)的低 - 低空间滤波帧(LL),基于 所述运动矢量场的集合导致包括N个时间滤波的帧的第一分解级的第一时间子带(ST 1)。 然后,将包括空间滤波步骤,运动估计步骤和运动补偿滤波步骤的序列迭代在时域和空间域中具有最低频率的帧上,直到每个时间子带的一个低时频频率帧为止。