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1. 发明授权

US08443269B2 System and method for handling forward error correction code blocks in a receiver 有权
标题翻译：用于处理接收机中前向纠错码块的系统和方法
公开(公告)号：US08443269B2
公开(公告)日：2013-05-14
申请号：US12939656
申请日：2010-11-04
申请人： Sheng-Lung Lee
发明人： Sheng-Lung Lee
IPC分类号： G06F11/00
CPC分类号： H04L1/008 , H04L1/0057
摘要： A receiver apparatus can identify a plurality of patterns corresponding to scrambled synchronization bytes of a transport stream in a number of successive signal frames containing FEC code blocks, determine a pattern distribution into which most of the patterns identified in the successive signal frames map, and generate a synchronization signal locked to a distribution of the FEC code blocks associated with the pattern distribution. With this synchronization signal, FEC code blocks can be timely handled in a reliable manner through a FEC decoder, making the receiver apparatus more efficient and robust. In other embodiments, methods of handling FEC code blocks in a receiver apparatus are also described.
摘要翻译：接收机设备可以识别与包含FEC码块的多个连续信号帧中的传输流的加扰同步字节相对应的多个模式，确定在连续信号帧中所标识的大部分模式映射到的模式分布，并生成锁定到与模式分布相关联的FEC码块的分布的同步信号。利用该同步信号，FEC码块可以通过FEC解码器以可靠的方式被及时处理，使得接收机设备更有效和鲁棒。在其他实施例中，还描述了在接收机设备中处理FEC码块的方法。

2. 发明授权

US08390501B2 Successive approximation register ADC with a window predictive function 有权
标题翻译：具有窗口预测功能的逐次逼近寄存器ADC
公开(公告)号：US08390501B2
公开(公告)日：2013-03-05
申请号：US13096908
申请日：2011-04-28
申请人： Soon-Jyh Chang , Guan-Ying Huang , Chun-Cheng Liu , Chung-Ming Huang , Jin-Fu Lin , Chih-Haur Huang
发明人： Soon-Jyh Chang , Guan-Ying Huang , Chun-Cheng Liu , Chung-Ming Huang , Jin-Fu Lin , Chih-Haur Huang
IPC分类号： H03M1/34
CPC分类号： H03M1/462 , H03M1/466
摘要： A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.
摘要翻译：公开了逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。第一和第二电容器DAC分别接收第一和第二输入信号。第一粗略比较器将第一电容器DAC的输出与窗口参考电压进行比较，第二粗略比较器将第二电容器DAC的输出与窗口参考电压进行比较，精细比较器将第一电容器DAC的输出与第二电容DAC的输出。 SAR控制器接收第一和第二粗略比较器的输出，以确定第一和第二电容器DAC的输出是否在由窗口参考电压确定的预测窗口内。当第一电容器DAC和第二电容器DAC的输出被确定为在预测窗口内时，SAR控制器绕过至少一个SAR模数转换阶段。 SAR控制器解码第一和第二粗略比较器和精细比较器的输出，以获得SAR ADC的转换输出。

3. 发明授权

US08345070B2 Apparatus and method for frame rate up conversion 有权
标题翻译：用于帧率转换的装置和方法
公开(公告)号：US08345070B2
公开(公告)日：2013-01-01
申请号：US12481822
申请日：2009-06-10
申请人： Wei-Ting Suen , Ling-Hsiu Huang , Lin-Kai Bu
发明人： Wei-Ting Suen , Ling-Hsiu Huang , Lin-Kai Bu
IPC分类号： G09G5/10
CPC分类号： G09G3/3611 , G09G2320/0252 , G09G2320/0261 , G09G2320/10 , G09G2340/0435 , G09G2340/16
摘要： A method for frame rate up conversion. The method is executed by a frame rate up-converter. The frame rate up-converter receives a plurality of consecutive input video frames and detects luminance information for a current frame. The frame rate up-converter generates a first output frame according to the luminance information for the current frame and a preceding frame before the current frame and generates a second output frame according to the luminance information for the current frame and a succeeding frame after the current frame, wherein the second output frame is outputted after the first output frame.
摘要翻译：一种帧速率转换的方法。该方法由帧速率上变频器执行。帧率上变换器接收多个连续的输入视频帧并检测当前帧的亮度信息。帧速上变频器根据当前帧的亮度信息和当前帧之前的帧产生第一输出帧，并根据当前帧的亮度信息和当前帧之后的后续帧产生第二输出帧帧，其中在第一输出帧之后输出第二输出帧。

4. 发明授权

US08340239B2 Decoder and method for adaptively generating a clock window 有权
标题翻译：用于自适应地生成时钟窗口的解码器和方法
公开(公告)号：US08340239B2
公开(公告)日：2012-12-25
申请号：US12651983
申请日：2010-01-04
申请人： Tien-Ju Tsai
发明人： Tien-Ju Tsai
IPC分类号： H04L7/02
CPC分类号： H04N7/0352
摘要： A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.
摘要翻译：解码器和相关方法自适应地生成时钟窗口。检测水平同步信号的下降沿，确定实际帧码与预定帧码之间的时间差。然后，基于下降沿和时间差自适应地确定时钟窗口的开始和结束，使得可以在生成的时钟窗口内执行通过接收的时钟输入信号的符号定时恢复。

5. 发明授权

US08334834B2 Backlight control system and method 有权
标题翻译：背光控制系统及方法
公开(公告)号：US08334834B2
公开(公告)日：2012-12-18
申请号：US12242702
申请日：2008-09-30
申请人： Shing-Chia Chen
发明人： Shing-Chia Chen
IPC分类号： G09G3/36
CPC分类号： G09G3/3406 , G09G2320/064 , G09G2320/0646 , G09G2340/16 , G09G2360/16
摘要： A backlight control system and method are disclosed. An overdrive device modifies a backlight duty signal according to a current-frame backlight duty signal and a previous-frame backlight duty signal. In one embodiment, the overdrive device is implemented with a lookup table that outputs the modified backlight duty signal. The backlight driven by the modified backlight duty signal then emits light to a display panel, thereby increasing a response time of the backlight.
摘要翻译：公开了一种背光控制系统和方法。过驱动装置根据当前帧背光负载信号和前一帧背光占空比信号来修改背光负载信号。在一个实施例中，过驱动装置用输出修改的背光占空比信号的查找表来实现。由改进的背光负载信号驱动的背光然后向显示面板发光，从而增加背光的响应时间。

6. 发明申请

US20120274626A1 Stereoscopic Image Generating Apparatus and Method 审中-公开
标题翻译：立体图像发生装置及方法
公开(公告)号：US20120274626A1
公开(公告)日：2012-11-01
申请号：US13097528
申请日：2011-04-29
申请人： Chia-Ming Hsieh
发明人： Chia-Ming Hsieh
IPC分类号： G06T15/08
CPC分类号： G06T5/50 , G06T7/50 , H04N13/111 , H04N13/128
摘要： A depth map generating device. A first depth information extractor extracts a first depth information from a main two dimensional (2D) image according to a first algorithm and generates a first depth map corresponding to the main 2D image. A second depth information extractor extracts a second depth information from a sub 2D image according to a second algorithm and generates a second depth map corresponding to the sub 2D image. A mixer mixes the first depth map and the second depth map according to adjustable weighting factors to generate a mixed depth map. The mixed depth map is utilized for converting the main 2D image to a set of three dimensional (3D) images.
摘要翻译：深度图生成装置。第一深度信息提取器根据第一算法从主二维（2D）图像提取第一深度信息，并生成对应于主2D图像的第一深度图。第二深度信息提取器根据第二算法从子2D图像中提取第二深度信息，并产生对应于子2D图像的第二深度图。混合器根据可调加权因子混合第一深度图和第二深度图以产生混合深度图。混合深度图用于将主2D图像转换成一组三维（3D）图像。

7. 发明授权

US08289265B2 Backlight controller, display device using the same and method for controlling backlight module 有权
标题翻译：背光控制器，使用相同的显示设备和控制背光模块的方法
公开(公告)号：US08289265B2
公开(公告)日：2012-10-16
申请号：US12173234
申请日：2008-07-15
申请人： Kuo-Liang Shen , Chien-Chung Chen , Shing-Chia Chen
发明人： Kuo-Liang Shen , Chien-Chung Chen , Shing-Chia Chen
IPC分类号： G09G3/36
CPC分类号： G09G3/3406 , G09G2320/062
摘要： A backlight controller, a display device using the same and a method for controlling a backlight module are provided. The backlight controller includes a temporal weighting module and a dimming controlling module. The temporal weighting module calculates a weight sum of a first backlight luminance provided in a current frame and a target backlight luminance to serve as an adjusted backlight luminance. The target backlight luminance is obtained according to an image content of the current frame. The dimming controlling module increases or decreases the adjusted backlight luminance by a step value according to the target backlight luminance and generates a second backlight luminance provided in a next frame. Therefore, a backlight luminance of the backlight module not only can be smoothly adjusted to the target backlight luminance at high speed for avoiding backlight flicker, but also can be adaptive to image content for saving electric power consumption.
摘要翻译：提供了一种背光控制器，使用其的显示装置和用于控制背光模块的方法。背光控制器包括时间加权模块和调光控制模块。时间加权模块计算当前帧中提供的第一背光亮度和目标背光亮度的权重和作为调整的背光亮度。根据当前帧的图像内容获得目标背光亮度。调光控制模块根据目标背光亮度将调整后的背光亮度增加或减小步长值，并产生下一帧中提供的第二背光亮度。因此，为了避免背光闪烁，背光源模块的背光亮度不仅可以高速地平滑地调整到目标背光亮度，而且可以适应于用于节省电力消耗的图像内容。

8. 发明申请

US20120256962A1 Video Processing Apparatus and Method for Extending the Vertical Blanking Interval 审中-公开
标题翻译：视频处理装置和扩展垂直消隐间隔的方法
公开(公告)号：US20120256962A1
公开(公告)日：2012-10-11
申请号：US13081798
申请日：2011-04-07
申请人： Shang-Chieh Wen
发明人： Shang-Chieh Wen
IPC分类号： G09G5/00
CPC分类号： G09G5/373 , G09G3/003 , G09G5/18 , G09G5/391 , G09G2340/04 , G09G2340/12 , G09G2350/00 , H04N7/0122 , H04N13/139 , H04N13/183 , H04N13/341
摘要： A video processing apparatus. A first scaling module receives original images according to an original pixel clock and performs adjustments on the original images according to a first scaling ratio to generate first scaled images. A frame buffer buffers the first scaled images. A controller controls the frame buffer to receive the first scaled images according to a first pixel clock and output the first scaled images according to a second pixel clock. A second scaling module receives the first scaled images and performs adjustments on the first scaled images according to a second scaling ratio to generate second scaled images. A length of a vertical blanking interval of the second scaled images is longer than a length of a vertical blanking interval of the original images.
摘要翻译：视频处理装置。第一缩放模块根据原始像素时钟接收原始图像，并根据第一缩放比例对原始图像执行调整，以产生第一缩放图像。帧缓冲器缓冲第一个缩放的图像。控制器控制帧缓冲器以根据第一像素时钟接收第一缩放图像，并根据第二像素时钟输出第一缩放图像。第二缩放模块接收第一缩放图像，并根据第二缩放比例对第一缩放图像执行调整，以产生第二缩放图像。第二缩放图像的垂直消隐间隔的长度比原始图像的垂直消隐间隔的长度长。

9. 发明授权

US08281208B2 Receiver with capability of correcting error 有权
标题翻译：接收机具有校正误差的能力
公开(公告)号：US08281208B2
公开(公告)日：2012-10-02
申请号：US12791801
申请日：2010-06-01
申请人： Tien-Ju Tsai
发明人： Tien-Ju Tsai
IPC分类号： H03M13/00
CPC分类号： H04L1/0065 , H03M13/19 , H03M13/2933 , H03M13/6577 , H04L1/0045
摘要： A receiver with capability of correcting error is disclosed. A soft slicer generates quantized data and associated soft data. A decoder with error recovery generates decoded quantized data and a soft sequence, and is capable of correcting one bit of the quantized data. A serial-to-parallel (S/P) converter with code corrector generates parallel data, and is capable of correcting two bits of de-scrambled data bits.
摘要翻译：公开了一种具有校正误差能力的接收机。软切片器产生量化数据和相关联的软数据。具有错误恢复的解码器产生解码的量化数据和软序列，并且能够校正量化数据的一位。具有码校正器的串并行（S / P）转换器产生并行数据，并且能够校正两位解扰数据位。

10. 发明申请

US20120230453A1 CHANNEL ESTIMATION AND SYMBOL BOUNDARY DETECTION METHOD 有权
标题翻译：通道估计和符号边界检测方法
公开(公告)号：US20120230453A1
公开(公告)日：2012-09-13
申请号：US13159306
申请日：2011-06-13
申请人： PEI-JUN SHIH , CHING-SHENG NI , SHIN-SHIUAN CHENG
发明人： PEI-JUN SHIH , CHING-SHENG NI , SHIN-SHIUAN CHENG
IPC分类号： H04L27/06 , H04B1/10
CPC分类号： H04L25/0212 , H04L25/0204 , H04L25/0224 , H04L27/2663 , H04L27/2665 , H04L27/2675 , H04L27/2695
摘要： A channel estimation method for use with a received signal by a receiver is disclosed. The received signal comprises multiple data bursts which are transmitted to the receiver via multiple path channels, with each of the data bursts having a plurality of preamble symbols which are decoded. The channel estimation method includes the following steps: firstly, at least one correlation pattern is generated according to the decoded preamble symbols. Then, a cross correlation of the correlation pattern with the received signal is performed to yield at least one correlation result of channel impulse response (CIR). Wherein, the symbol boundary of the received signal is decided according to the correlation result.
摘要翻译：公开了一种与接收机接收的信号一起使用的信道估计方法。所接收的信号包括多个数据脉冲串，其经由多个路径信道被发送到接收机，其中每个数据脉冲串具有被解码的多个前导码符号。信道估计方法包括以下步骤：首先，根据解码的前导符号生成至少一个相关模式。然后，执行相关模式与接收信号的互相关，以产生信道脉冲响应（CIR）的至少一个相关结果。其中，根据相关结果确定接收信号的符号边界。

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