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1. 发明申请

US20090310616A1 SWITCH FABRIC PRIMITIVES 有权
标题翻译：开关织物主体
公开(公告)号：US20090310616A1
公开(公告)日：2009-12-17
申请号：US12483662
申请日：2009-06-12
申请人： Uri Cummings , Zhi-Hern Loh
发明人： Uri Cummings , Zhi-Hern Loh
IPC分类号： H04L12/56
CPC分类号： H04L49/254 , H04L49/109
摘要： Techniques are described for optimizing broadcast and collect primitives in switch fabrics.
摘要翻译：描述了用于在交换结构中优化广播和收集原语的技术。

2. 发明授权

US07274710B2 Asynchronous crossbar with deterministic or arbitrated control 有权
标题翻译：具有确定性或仲裁控制的异步交叉开关
公开(公告)号：US07274710B2
公开(公告)日：2007-09-25
申请号：US10237406
申请日：2002-09-06
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： H04J3/02
CPC分类号： H04Q3/0004
摘要： Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.
摘要翻译：描述了涉及可操作以根据路由控制信息将数据从第一数量的输入信道中的任何一个路由到第二数量的输出信道中的任一个的交叉开关的方法和装置。输入通道和输出通道的每个组合对应于多个链接中的一个。交叉开关电路可操作地以确定性的方式在每个链路上路由数据，从而保留由路由控制信息表示的部分排序。不同链接的事件是不相关的。

3. 发明授权

US07260753B2 Methods and apparatus for providing test access to asynchronous circuits and systems 有权
标题翻译：用于提供对异步电路和系统的测试访问的方法和装置
公开(公告)号：US07260753B2
公开(公告)日：2007-08-21
申请号：US10628074
申请日：2003-07-25
申请人： Michel A. Moacanin , Jeremy Boulton , Steven Novak
发明人： Michel A. Moacanin , Jeremy Boulton , Steven Novak
IPC分类号： G01R31/28 , H03L7/00
CPC分类号： G01R31/318594 , G01R31/31726 , G11C2029/5602
摘要： Methods and apparatus are described for providing test access by synchronous test equipment to an asynchronous circuit. Synchronous-to-asynchronous (S2A) conversion circuitry is operable to receive synchronous input data serially from the synchronous test equipment and convert the synchronous input data to asynchronous input data. Asynchronous logic is operable to transmit the asynchronous input data to a first test register in the asynchronous circuit, and to transmit asynchronous output data received from a second test register in the asynchronous circuit. The asynchronous output data results from application of the asynchronous input data to the asynchronous circuit. Operation of the asynchronous logic is synchronized at least in part with a clock signal associated with the synchronous test equipment. Asynchronous-to-synchronous (A2S) conversion circuitry is operable to receive the asynchronous output data from the asynchronous logic, convert the asynchronous output data to synchronous output data, and serially transmit the synchronous output data to the synchronous test equipment.
摘要翻译：描述了用于通过同步测试设备向异步电路提供测试访问的方法和装置。同步到异步（S2A）转换电路可操作以从同步测试设备串行接收同步输入数据，并将同步输入数据转换为异步输入数据。异步逻辑可操作地将异步输入数据发送到异步电路中的第一测试寄存器，并且发送从异步电路中的第二测试寄存器接收的异步输出数据。异步输出数据的结果是将异步输入数据应用于异步电路。异步逻辑的操作至少部分地与与同步测试设备相关联的时钟信号同步。异步到同步（A2S）转换电路可操作以从异步逻辑接收异步输出数据，将异步输出数据转换为同步输出数据，并将同步输出数据串行发送到同步测试设备。

4. 发明授权

US07161828B2 Asynchronous static random access memory 有权
标题翻译：异步静态随机存取存储器
公开(公告)号：US07161828B2
公开(公告)日：2007-01-09
申请号：US11200722
申请日：2005-08-09
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner.
摘要翻译：提供了包括多个SRAM状态元件和SRAM环境电路的静态随机存取存储器（SRAM）。 SRAM环境电路可操作以与外部异步电路接口，并且能够以延迟不敏感的方式读取和写入SRAM状态元件。

5. 发明授权

US08495543B2 Multi-level domino, bundled data, and mixed templates 有权
标题翻译：多级多米诺骨牌，捆绑数据和混合模板
公开(公告)号：US08495543B2
公开(公告)日：2013-07-23
申请号：US12527187
申请日：2009-06-17
申请人： Georgios Dimou , Peter A. Beerel , Andrew Lines
发明人： Georgios Dimou , Peter A. Beerel , Andrew Lines
IPC分类号： G06F17/50
CPC分类号： H03K19/096 , G06F17/505
摘要： Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages. The data path and controller interact through a small number of key control signals.
摘要翻译：描述了用于生成用于实现的异步电路（例如，以一个或多个网表的形式）的技术，例如在集成电路/芯片中。实施例涉及异步多级多米诺骨牌设计模板和几种变型，包括多米诺骨牌和单轨数据逻辑的混合。模板可以提供高吞吐量，低延迟和面积效率。多层次的多米诺骨牌模板被划分为流水线阶段，其中每个阶段由潜在的多层次的多米诺骨牌组成，由单个控制器控制，通过握手与其他控制器进行通信。每个阶段由两部分组成：数据路径和控制路径。数据路径实现计算逻辑，组合和顺序使用有效的双轨多米诺骨牌逻辑。控制路径实现了唯一的四相握手，以确保流水线阶段之间的正确性和逻辑依赖性的保持。数据路径和控制器通过少量关键控制信号进行交互。

6. 发明授权

US08098574B2 Global ports in multi-switch systems 有权
标题翻译：多交换机系统中的全局端口
公开(公告)号：US08098574B2
公开(公告)日：2012-01-17
申请号：US12198347
申请日：2008-08-26
申请人： Robert Southworth , Uri Cummings , Zhi-Hern Loh
发明人： Robert Southworth , Uri Cummings , Zhi-Hern Loh
IPC分类号： G01R31/08
CPC分类号： H04L49/3009 , H04L41/0677 , H04L49/351
摘要： Global ports are supported in multi-switch systems having arbitrary topologies. In some implementations, global ports are implemented in a manner which makes the switch system robust in the face of link failure. In specific Ethernet implementations, global ports enable flooding, learning, forwarding, and link aggregation across the switch system.
摘要翻译：全局端口在具有任意拓扑的多交换机系统中得到支持。在一些实现中，全局端口以使得交换机系统在面对链路故障时稳健的方式来实现。在特定的以太网实现中，全局端口可以实现跨交换系统的泛洪，学习，转发和链路聚合。

7. 发明申请

US20110164496A1 FLOW AND CONGESTION CONTROL IN SWITCH ARCHITECTURES FOR MULTI-HOP, MEMORY EFFICIENT FABRICS 有权
标题翻译：多用途记忆效能织物开关结构中的流量控制与控制
公开(公告)号：US20110164496A1
公开(公告)日：2011-07-07
申请号：US12986031
申请日：2011-01-06
申请人： Zhi-Hern Loh , Michael Davies , Uri Cummings
发明人： Zhi-Hern Loh , Michael Davies , Uri Cummings
IPC分类号： H04L12/26
CPC分类号： H04L47/10 , H04L45/302 , H04L47/11 , H04L47/125 , H04L49/103 , H04L49/205 , H04L49/254 , H04L49/508
摘要： A shared memory switch and switch fabric architecture are described which employ partitions of the shared memory to implement multiple, independent virtual congestion domains, thereby allowing congestion to be handled for different classes of traffic independently.
摘要翻译：描述共享存储器交换机和交换矩阵体系结构，其使用共享存储器的分区来实现多个独立的虚拟拥塞域，从而允许独立地针对不同类别的业务处理拥塞。

8. 发明申请

US20110029941A1 MULTI-LEVEL DOMINO, BUNDLED DATA, AND MIXED TEMPLATES 有权
标题翻译：多层面多米诺，填充数据和混合模板
公开(公告)号：US20110029941A1
公开(公告)日：2011-02-03
申请号：US12527187
申请日：2009-06-17
申请人： Georgios Dimou , Peter A. Beerel , Andrew Lines
发明人： Georgios Dimou , Peter A. Beerel , Andrew Lines
IPC分类号： G06F17/50
CPC分类号： H03K19/096 , G06F17/505
摘要： Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages. The data path and controller interact through a small number of key control signals.
摘要翻译：描述了用于生成用于实现的异步电路（例如，以一个或多个网表的形式）的技术，例如在集成电路/芯片中。实施例涉及异步多级多米诺骨牌设计模板和几种变型，包括多米诺骨牌和单轨数据逻辑的混合。模板可以提供高吞吐量，低延迟和面积效率。多层次的多米诺骨牌模板被划分为流水线阶段，其中每个阶段由潜在的多层次的多米诺骨牌组成，由单个控制器控制，通过握手与其他控制器进行通信。每个阶段由两部分组成：数据路径和控制路径。数据路径实现计算逻辑，组合和顺序使用有效的双轨多米诺骨牌逻辑。控制路径实现了唯一的四相握手，以确保流水线阶段之间的正确性和逻辑依赖性的保持。数据路径和控制器通过少量关键控制信号进行交互。

9. 发明申请

US20100161892A1 PSEUDO DUAL-PORTED SRAM 有权
标题翻译： PSEUDO双面SRAM
公开(公告)号：US20100161892A1
公开(公告)日：2010-06-24
申请号：US12340022
申请日：2008-12-19
申请人： Jonathan Dama , Andrew Lines
发明人： Jonathan Dama , Andrew Lines
IPC分类号： G06F12/00
CPC分类号： G11C8/16 , G11C7/1075 , G11C8/18
摘要： A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory capable of reading and writing any two arbitrary addresses on the same cycle.
摘要翻译：描述了一种存储器，其包括由通过并行读和写总线连接的多个单端口存储器组成的主存储器阵列，以及等同于单个双端口存储器组的边带存储器。控制逻辑和标签状态有助于访问主存储器和边带存储器的模式，使得存储器像完全配置的双端口存储器那样执行，其能够在相同周期上读取和写入任意两个任意地址。

10. 发明申请

US20050276095A1 Asynchronous static random access memory 有权
标题翻译：异步静态随机存取存储器
公开(公告)号：US20050276095A1
公开(公告)日：2005-12-15
申请号：US11200722
申请日：2005-08-09
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： G11C20060101 , G11C11/00 , G11C11/413 , G11C15/00
CPC分类号： G11C11/413
摘要： A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner.
摘要翻译：提供了包括多个SRAM状态元件和SRAM环境电路的静态随机存取存储器（SRAM）。 SRAM环境电路可操作以与外部异步电路接口，并且能够以延迟不敏感的方式读取和写入SRAM状态元件。

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