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1. 发明授权

US07437702B2 Method for making mask in process of fabricating semiconductor device 失效
标题翻译：在制造半导体器件的过程中制造掩模的方法
公开(公告)号：US07437702B2
公开(公告)日：2008-10-14
申请号：US11316876
申请日：2005-12-27
申请人： Mun Hoe Do
发明人： Mun Hoe Do
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for making a mask in a process of fabricating a semiconductor device is disclosed, in which one database is classified into an SRAM block and a random logic block so that OPC is separately performed for the SRAM block and the random logic block, thereby improving performance of the OPC. The method includes dividing an input database into an SRAM block and a random logic block, respectively performing optical proximity correction (OPC) for the SRAM block and the random logic block, and combining the SRAM block to the random logic block.
摘要翻译：公开了一种在制造半导体器件的过程中制造掩模的方法，其中一个数据库分为SRAM块和随机逻辑块，以便为SRAM块和随机逻辑块分别执行OPC，从而改进 OPC的性能。该方法包括将输入数据库划分为SRAM块和随机逻辑块，分别对SRAM块和随机逻辑块执行光学邻近校正（OPC），并将SRAM块组合到随机逻辑块。

2. 发明申请

US20070126050A1 Flash memory cell and fabrication method thereof 审中-公开
标题翻译：闪存单元及其制造方法
公开(公告)号：US20070126050A1
公开(公告)日：2007-06-07
申请号：US11319410
申请日：2005-12-29
申请人： Sung Jin Kim
发明人： Sung Jin Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： A flash memory cell transistor is presented that includes a stacked structure of successively formed tunnel oxide layer, floating gate, inter-gate insulating layer and control gate on a semiconductor substrate, an insulating thin film formed on a first sidewall of the stacked structure, and an access gate formed on the first sidewall of the stacked structure while interposing the insulating thin film. A drain region is formed in a first region of the substrate in which the first region is exposed by the floating gate and a source region is formed in a second region of the substrate in which the second region is exposed by the access gate. The access gate overlaps, along the vertical direction of the stacked structure, the control gate and the floating gate.
摘要翻译：提出一种闪存单元晶体管，其包括在半导体衬底上形成的连续形成的隧道氧化物层，浮置栅极，栅极间绝缘层和控制栅极的堆叠结构，形成在层叠结构的第一侧壁上的绝缘薄膜，以及形成在堆叠结构的第一侧壁上的入口门，同时插入绝缘薄膜。在衬底的第一区域中形成漏极区域，其中第一区域被浮置栅极暴露，并且源极区域形成在衬底的第二区域中，其中第二区域被存取栅极暴露。存取栅极沿堆叠结构的垂直方向重叠控制栅极和浮动栅极。

3. 发明申请

US20070120200A1 MOS transistor having double gate and manufacturing method thereof 审中-公开
标题翻译：具有双栅极的MOS晶体管及其制造方法
公开(公告)号：US20070120200A1
公开(公告)日：2007-05-31
申请号：US11320824
申请日：2005-12-30
申请人： Hyung Yun
发明人： Hyung Yun
IPC分类号： H01L29/76
CPC分类号： H01L29/66772 , H01L29/78648
摘要： There are provided a MOS transistor having a double gate and a manufacturing method thereof. The MOS transistor includes a substrate on which an insulating layer is formed, a first gate embedded in the insulating layer, in which the top surface of the first gate is exposed, a first gate oxide layer formed on the insulating layer and the first gate, a silicon layer formed on the first gate oxide layer, a source region and a drain region formed in the silicon layer to be in contact with the first gate oxide layer, a second gate oxide layer formed on the silicon layer to be in contact with the source and drain regions, and a second gate formed on the second gate oxide layer disposed between the source region and the drain region.
摘要翻译：提供具有双栅极的MOS晶体管及其制造方法。 MOS晶体管包括其上形成有绝缘层的衬底，第一栅极的顶表面暴露在绝缘层中的第一栅极，形成在绝缘层和第一栅极上的第一栅氧化层，形成在所述第一栅极氧化物层上的硅层，形成在所述硅层中的与所述第一栅极氧化物层接触的源极区域和漏极区域，形成在所述硅层上以与所述第一栅极氧化物层接触的第二栅极氧化物层源极和漏极区，以及形成在设置在源极区和漏极区之间的第二栅极氧化物层上的第二栅极。

4. 发明申请

US20070102751A1 Non-volatile memory device and method of manufacturing the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070102751A1
公开(公告)日：2007-05-10
申请号：US11320588
申请日：2005-12-30
申请人： Sang-Bum Lee
发明人： Sang-Bum Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/42344 , H01L29/66833 , H01L29/7926
摘要： A non-volatile memory device and a method of manufacturing the same where the non-volatile memory device is easily applicable to higher integration of a semiconductor device by reducing a cell size while assuring storage capacities required for operations of a device. The non-volatile memory device includes a semiconductor substrate in which an active region is defined by an isolation layer and a protruding portion is formed on the active region, a source region formed on the protruding portion, first and second gates formed at both sidewalls of the protruding portion and the source region, first and second drain regions formed in the active region at the outside of the first and second gates, and an insulation layer formed between the first and second gates and the protruding portion and the source region.
摘要翻译：一种非易失性存储器件及其制造方法，其中非易失性存储器件通过减小电池尺寸而容易地应用于半导体器件的更高集成度，同时确保器件的操作所需的存储容量。非易失性存储器件包括其中有源区由隔离层限定并且在有源区上形成突出部分的半导体衬底，形成在突出部分上的源极区域，形成在两个侧壁上的第一和第二栅极突出部分和源极区域，形成在第一和第二栅极外部的有源区中的第一和第二漏极区域以及形成在第一和第二栅极与突出部分和源极区域之间的绝缘层。

5. 发明申请

US20070102716A1 Image sensor and fabricating method thereof 审中-公开
标题翻译：图像传感器及其制造方法
公开(公告)号：US20070102716A1
公开(公告)日：2007-05-10
申请号：US11320948
申请日：2005-12-30
申请人： Sang Kim
发明人： Sang Kim
IPC分类号： H01L33/00
CPC分类号： H01L27/14632 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14685 , H01L27/14687
摘要： An image sensor and fabricating method thereof enable total photoelectric conversion without light loss by enhancing surface uniformity of a microlens in each area of the microlens. The method includes the steps of forming a sublayer including a photodiode, a thin film transistor and metal lines on a substrate including a pad area and a cell area, forming a first planarizing layer on the sublayer, forming a plurality of color separating layers on the first planarizing layer within the cell area, forming a second planarizing layer on the first planarizing layer including at least one of the plurality of color separating layers in the cell area, forming a plurality of microlenses on the second planarizing layer to overlap the plurality of color separating layers, respectively, and forming a capping layer on the second planarizing layer to fill gaps between the plurality of microlenses.
摘要翻译：图像传感器及其制造方法通过增强微透镜的每个区域中的微透镜的表面均匀性，能够实现全光电转换而不发生光损失。该方法包括以下步骤：在包括衬垫区域和单元区域的衬底上形成包括光电二极管，薄膜晶体管和金属线的子层，在子层上形成第一平坦化层，在其上形成多个分色层在所述单元区域内的第一平坦化层，在所述第一平坦化层上形成包括所述单元区域中的所述多个颜色分离层中的至少一个的第二平坦化层，在所述第二平坦化层上形成多个微透镜以与所述多个颜色重叠分离层，并在第二平坦化层上形成覆盖层以填充多个微透镜之间的间隙。

6. 发明申请

US20070091303A1 Device for detecting contamination of lens in exposure device 审中-公开
标题翻译：用于检测曝光装置中的透镜污染的装置
公开(公告)号：US20070091303A1
公开(公告)日：2007-04-26
申请号：US11320738
申请日：2005-12-30
申请人： Jin Kim
发明人： Jin Kim
IPC分类号： G01N21/00
CPC分类号： G01N21/94 , G01N2021/157 , G01N2021/945
摘要： A device for detecting contamination of a lens in an exposure device in which a sample for detecting contamination is formed of the same material as that of the lens and transmittance of the sample is detected to sense a contamination level of the lens.
摘要翻译：用于检测曝光装置中的透镜污染的装置，其中用于检测污染物的样品由与透镜相同的材料形成，并且检测样品的透射率以感测透镜的污染水平。

7. 发明申请

US20070066030A1 METHOD OF MANUFACTURING AN ISOLATION LAYER OF A FLASH MEMORY 有权
标题翻译：制造闪存存储器隔离层的方法
公开(公告)号：US20070066030A1
公开(公告)日：2007-03-22
申请号：US11320580
申请日：2005-12-30
申请人： Dong-Oog Kim
发明人： Dong-Oog Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： A method including forming a first mask material layer on a semiconductor substrate in order to mask a cell region and to not mask a peripheral circuit region. The method further includes forming a second mask material layer on an entire surface of the substrate in the cell region and peripheral circuit region, simultaneously forming a trench having a first depth in the cell region and a trench having a second depth in the peripheral circuit region, where the second depth is greater than the first depth. The method also includes filling an insulation layer into an entire surface of the substrate including trenches, planarizing the insulation material layer and the second mask material layer to a degree that the first mask material layer is exposed, and respectively forming an STI isolation layer in both the cell region and the peripheral circuit region by removing the first and second mask material layer.
摘要翻译：一种方法，包括在半导体衬底上形成第一掩模材料层以掩蔽单元区域并且不掩蔽外围电路区域。该方法还包括在单元区域和外围电路区域中在基板的整个表面上形成第二掩模材料层，同时形成在单元区域中具有第一深度的沟槽和在外围电路区域中具有第二深度的沟槽，其中第二深度大于第一深度。该方法还包括将绝缘层填充到包括沟槽的衬底的整个表面中，将绝缘材料层和第二掩模材料层平坦化到第一掩模材料层暴露的程度，并且在两者中分别形成STI隔离层通过去除第一和第二掩模材料层来形成单元区域和外围电路区域。

8. 发明申请

US20070059937A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070059937A1
公开(公告)日：2007-03-15
申请号：US11320624
申请日：2005-12-30
申请人： Jae Kang
发明人： Jae Kang
IPC分类号： H01L21/311
CPC分类号： H01L21/32139 , H01L21/0276
摘要： A method for manufacturing a semiconductor device deposits a plurality of bottom antireflective coating films to prevent a standing wave caused by a light source of a short wavelength in forming a fine pattern. The method includes forming a pattern formation layer on an entire surface of a wafer, forming two or more bottom antireflective coating films on the pattern formation layer, forming a photoresist film pattern on a predetermined region of the bottom antireflective coating films, etching the bottom antireflective coating films using the photoresist film pattern as a mask, forming sidewall spacers at sides of the photoresist film pattern, and etching the pattern formation layer using the sidewall spacers and the photoresist film pattern as masks.
摘要翻译：半导体器件的制造方法沉积多个底部抗反射涂膜以防止由形成微细图案的短波长的光源引起的驻波。该方法包括在晶片的整个表面上形成图形形成层，在图案形成层上形成两个或更多个底部抗反射涂层，在底部抗反射涂膜的预定区域上形成光刻胶膜图案，蚀刻底部抗反射使用光致抗蚀剂膜图案作为掩模的涂膜，在光致抗蚀剂膜图案的侧面形成侧壁间隔物，并使用侧壁间隔物和光致抗蚀剂膜图案作为掩模蚀刻图案形成层。

9. 发明申请

US20070056856A1 Apparatus and method for electrically contacting wafer in electronic chemical plating cell 审中-公开
标题翻译：电子化学镀电池中晶片电接触的装置和方法
公开(公告)号：US20070056856A1
公开(公告)日：2007-03-15
申请号：US11320621
申请日：2005-12-30
申请人： Ji Hong
发明人： Ji Hong
IPC分类号： C25D7/12
CPC分类号： C25D17/001 , C25D17/005 , H01L21/2885
摘要： An apparatus and method for electrically contacting a wafer in an electronic chemical plating cell includes a plating bath containing an electrolytic solution therein, an anode member arranged at a lower portion in the plating bath, a support member for arranging a wafer at an upper portion in the plating bath to face the anode member, a first cathode contact member electrically contacting an edge of the wafer, a second cathode contact member electrically contacting the center of the wafer, and a power supply electrically connected among the anode member, the first cathode contact member and the second cathode contact member to supply the power. Since resistance of a seed layer is reduced, it is possible to improve uniformity of the plating layer.
摘要翻译：用于电接触电子化学镀电池中的晶片的装置和方法包括其中包含电解液的镀浴，布置在镀浴中的下部的阳极构件，用于在上部设置晶片的支撑构件所述电镀浴面对所述阳极部件，与所述晶片的边缘电接触的第一阴极接触部件，与所述晶片的中心电接触的第二阴极接触部件与所述阳极部件，所述第一阴极接触部构件和第二阴极接触构件供电。由于种子层的电阻降低，可以提高镀层的均匀性。

10. 发明申请

US20070052005A1 Flash memory and a method of manufacturing the same 失效
标题翻译：闪存及其制造方法
公开(公告)号：US20070052005A1
公开(公告)日：2007-03-08
申请号：US11320606
申请日：2005-12-30
申请人： Sang-Woo Nam
发明人： Sang-Woo Nam
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L27/11521 , H01L29/7881
摘要： The present invention provides a method of manufacturing a flash memory device. The method includes forming a gate oxide layer on a semiconductor substrate, forming a floating gate including protrusions and depressions on its surface by patterning polysilicon deposited on the gate oxide layer, depositing a dielectric layer on the floating gate and the gate oxide layer, and forming a control gate by patterning polysilicon deposited on the dielectric layer.
摘要翻译：本发明提供一种制造闪速存储器件的方法。该方法包括在半导体衬底上形成栅极氧化层，在其表面上形成包括突起和凹陷的浮动栅极，通过图案化沉积在栅极氧化物层上的多晶硅，在浮动栅极和栅极氧化物层上沉积介电层，并形成通过图案化沉积在电介质层上的多晶硅的控制栅极。

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