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1. 发明授权

US08065504B2 Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor 有权
标题翻译：使用由指令地址索引的片上和片外查找表来控制处理器中的指令执行
公开(公告)号：US08065504B2
公开(公告)日：2011-11-22
申请号：US11004729
申请日：2004-12-02
申请人： John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Korbin S. Van Dyke , Shalesh Thusoo , Tiruvur R. Ramesh
发明人： John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Korbin S. Van Dyke , Shalesh Thusoo , Tiruvur R. Ramesh
IPC分类号： G06F9/30
CPC分类号： G06F9/45533
摘要： A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.
摘要翻译：微处理器芯片具有指令流水线电路和指令分类电路，它们将执行的指令分类为少量类并记录分类代码值。片上表具有对应于存储器的一系列地址的条目，并且被设计为保持在计算机的存储器中查看片外表的值的统计评估。查找电路被设计为从微处理器的基本指令处理周期的一部分获取片上表格中的条目。掩码至少部分由定时器设置的值。基于与所处理的指令的地址，掩码的当前值，记录的分类代码和片外表相对应的片上表项的值来控制指令流水线电路。

2. 发明授权

US07574065B2 Variable-length code decoder 有权
标题翻译：可变长度码解码器
公开(公告)号：US07574065B2
公开(公告)日：2009-08-11
申请号：US10865469
申请日：2004-06-10
申请人： Chad E. Fogg , Nital P. Patwa , Parin B. Dalal , Stephen C. Purcell , Korbin Van Dyke , Steve C. Hale
发明人： Chad E. Fogg , Nital P. Patwa , Parin B. Dalal , Stephen C. Purcell , Korbin Van Dyke , Steve C. Hale
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： H04N19/436 , H04N19/44 , H04N19/61 , H04N19/91
摘要： A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose registers. The general purpose registers store information used by at least two of the instructions.
摘要翻译：通过并行执行指令对串行接收的MPEG可变长度代码进行解码的方法。该方法包括执行单元，其包括多个流水线功能单元。功能单元并行执行至少两个指令。指令使用和共享通用寄存器。通用寄存器存储由至少两个指令使用的信息。

3. 发明授权

US07538765B2 Method and apparatus for generating hierarchical depth culling characteristics 有权
标题翻译：用于产生分层深度剔除特征的方法和装置
公开(公告)号：US07538765B2
公开(公告)日：2009-05-26
申请号：US10914949
申请日：2004-08-10
申请人： Larry D. Seiler , Laurent Lefebvre , Stephen L. Morein
发明人： Larry D. Seiler , Laurent Lefebvre , Stephen L. Morein
IPC分类号： G06T15/40
CPC分类号： G06T15/40
摘要： A method and apparatus for generating hierarchical depth culling characteristics includes determining a first minimum depth value and a first maximum depth value for a first graphical element. The graphical element may be a primitive. The first minimum depth value may be a minimum Z-plane depth of a pixel within the primitive and a first maximum depth value is a maximum Z-plane value for a pixel within the primitive. The method and apparatus further includes determining a second minimum depth value and a second maximum depth value for a second graphical element, which may be a tile. The method and apparatus further includes calculating an intersection depth range having an intersection minimum depth value and an intersection maximum depth value based on the intersection of the first minimum depth value and the first maximum depth value and the second minimum depth value and the second maximum depth value.
摘要翻译：一种用于产生分级深度剔除特征的方法和装置包括确定第一图形元素的第一最小深度值和第一最大深度值。图形元素可以是基元。第一最小深度值可以是基元内的像素的最小Z平面深度，并且第一最大深度值是该图元内的像素的最大Z平面值。所述方法和装置还包括确定可以是瓦片的第二图形元素的第二最小深度值和第二最大深度值。该方法和装置还包括基于第一最小深度值和第一最大深度值与第二最小深度值和第二最大深度的交点来计算具有交点最小深度值和交叉最大深度值的交点深度范围值。

4. 发明授权

US07483042B1 Video graphics module capable of blending multiple image layers 有权
标题翻译：能够混合多个图像层的视频图形模块
公开(公告)号：US07483042B1
公开(公告)日：2009-01-27
申请号：US09484123
申请日：2000-01-13
申请人： David I. J. Glen
发明人： David I. J. Glen
IPC分类号： G09G5/10
CPC分类号： G09G5/10 , G09G5/02 , G09G5/397 , G09G2340/10 , G09G2340/125
摘要： A video graphics module capable of blending multiple image layers includes a plurality of video graphic pipelines, each of which is operable to process a corresponding image layer. One of the video graphic pipelines processes a foremost image layer. For example, the foremost image layer may be a hardware cursor. The video graphics module also includes a blending module that is operably coupled to the plurality of video graphic pipelines. The blending module blends, in accordance with a blending convention (e.g., AND/Exclusive OR blending and/or alpha blending), the corresponding image layers of each pipeline in a predetermined blending order to produce an output image. The blending module blends the foremost image layer such that it appears in a foremost position with respect to the other image layers.
摘要翻译：能够混合多个图像层的视频图形模块包括多个视频图形流水线，每个视频图形流水线可操作以处理对应的图像层。视频图形管道之一处理最重要的图像层。例如，最前面的图像层可以是硬件光标。视频图形模块还包括可操作地耦合到多个视频图形管线的混合模块。混合模块根据混合惯例（例如，AND /异或混合和/或α混合）将预定混合顺序中的每个流水线的相应图像层混合以产生输出图像。混合模块混合最前面的图像层，使得其相对于其它图像层出现在最重要的位置。

5. 发明申请

US20080001972A1 METHOD AND APPARATUS FOR INDEPENDENT VIDEO AND GRAPHICS SCALING IN A VIDEO GRAPHICS SYSTEM 审中-公开
标题翻译：在视频图形系统中独立视频和图形缩放的方法和装置
公开(公告)号：US20080001972A1
公开(公告)日：2008-01-03
申请号：US11855676
申请日：2007-09-14
申请人： Edward Callway , Allen Porter , Chun-Chin Yeh , Philip Swan
发明人： Edward Callway , Allen Porter , Chun-Chin Yeh , Philip Swan
IPC分类号： G09G5/00
CPC分类号： G09G5/397 , G09G2320/0247 , G09G2340/0407 , G09G2340/125 , G09G2370/042
摘要： A method and apparatus for independent video and graphics scaling in a video graphics system is accomplished by receiving a video data stream, wherein the video data stream includes video data in a first format. A graphics data stream is also received, and the graphics data stream includes graphics data in a second format. The video data of the video data stream is scaled based on a ratio between the first format and a selected video format to produce a scaled video stream. Similarly, the graphics data of the graphics data stream is scaled based on a ratio between the second format and a selected graphics format in order to produce a scaled graphics stream. The scaled video stream and the scaled graphics stream are then merged to produce a video graphics output stream.
摘要翻译：通过接收视频数据流来实现视频图形系统中的独立视频和图形缩放的方法和装置，其中视频数据流包括第一格式的视频数据。还接收图形数据流，并且图形数据流包括第二格式的图形数据。基于第一格式和所选视频格式之间的比率来缩放视频数据流的视频数据，以产生缩放的视频流。类似地，图形数据流的图形数据基于第二格式和所选图形格式之间的比例进行缩放，以便产生缩放的图形流。缩放的视频流和缩放的图形流然后被合并以产生视频图形输出流。

6. 发明授权

US07277483B1 Method and apparatus for rate control for constant-bit-rate finite-buffer-size video encoder 有权
标题翻译：用于恒定位速率有限缓冲大小视频编码器速率控制的方法和装置
公开(公告)号：US07277483B1
公开(公告)日：2007-10-02
申请号：US09552761
申请日：2000-04-18
申请人： Stefan Eckart
发明人： Stefan Eckart
IPC分类号： H04N7/12 , H04N11/02
CPC分类号： H04N19/177 , H04N19/115 , H04N19/12 , H04N19/124 , H04N19/14 , H04N19/142 , H04N19/149 , H04N19/152 , H04N19/172 , H04N19/176 , H04N19/182 , H04N19/33 , H04N19/423 , H04N19/593 , H04N19/65
摘要： A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.
摘要翻译：描述了用于恒定比特率有限缓冲大小视频编码器的速率控制的方法和装置。通过基于帧内的大小来调整非帧内的大小来提供速率控制。实施滑动窗口方法以避免位于一组图像结束附近的非帧内帧的过度调整。使用基于像素值的绝对值的和的“功率”的测量。 “功率”测量用于调整全局复杂度值，用于调整帧的大小。全局复杂度值响应场景变化。本发明的实施例计算并使用L1距离和像素块复杂度来提供速率控制。本发明的一个实施例实现了多个比特预测器块。可以在图像级别，图像级别和像素块级别执行预测。当发生场景变化时，本发明的实施例重置全局复杂度参数。

7. 发明授权

US07275246B1 Executing programs for a first computer architecture on a computer of a second architecture 有权
标题翻译：在第二架构的计算机上执行第一台计算机体系结构的程序
公开(公告)号：US07275246B1
公开(公告)日：2007-09-25
申请号：US09239194
申请日：1999-01-28
申请人： John S. Yates, Jr. , Sandeep Nijhawan , Matthew F. Storch , Dale R. Jurich
发明人： John S. Yates, Jr. , Sandeep Nijhawan , Matthew F. Storch , Dale R. Jurich
IPC分类号： G06F9/46 , G06F9/455
CPC分类号： G06F9/45554 , G06F9/45541 , G06F9/45558 , G06F2009/45583
摘要： Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler. The entry exception, exit exception, entry handler, and exit handler are cooperatively designed to maintain an association between a one of the threads and an extended context of the thread through a context change induced by the operating system, the extended context including resources of the computer associated with the thread beyond those resources whose association with the thread is maintained by the operating system.
摘要翻译：在第二不同架构的计算机上执行以第一计算机的指令集编码的程序。操作系统维护一组并发线程中的每一个与线程上下文的一组计算机资源之间的关联。在不修改计算机的预先存在的操作系统的情况下，将在指定的入口点或指定条件下建立要在操作系统的每个条目上提出的入口异常。条目异常具有相关联的条目处理程序，其被编程为在将修改的上下文传送到操作系统之前，保存中断的线程的上下文并修改线程上下文。在操作系统的每次恢复之后建立恢复异常，补充指定条目之一。恢复异常具有相关联的退出处理程序，其被编程为恢复由相应执行的条目处理程序保存的上下文。入口异常，退出异常，条目处理程序和退出处理程序被协调地设计为通过由操作系统引发的上下文变化来维护线程中的一个线程和线程的扩展上下文之间的关联，扩展的上下文包括与线程相关联的计算机超出与该线程的关联的那些资源由操作系统维护。

8. 发明申请

US20070147512A1 METHOD AND APPARATUS FOR RATE CONTROL FOR CONSTANT-BIT-RATE-FINITE-BUFFER-SIZE VIDEO ENCODER 有权
标题翻译：用于恒定速率有限缓存大小视频编码器的速率控制的方法和装置
公开(公告)号：US20070147512A1
公开(公告)日：2007-06-28
申请号：US11681492
申请日：2007-03-02
申请人： Stefan Eckart
发明人： Stefan Eckart
IPC分类号： H04N11/04 , H04N7/12
CPC分类号： H04N19/177 , H04N19/115 , H04N19/12 , H04N19/124 , H04N19/14 , H04N19/142 , H04N19/149 , H04N19/152 , H04N19/172 , H04N19/176 , H04N19/182 , H04N19/33 , H04N19/423 , H04N19/593 , H04N19/65
摘要： A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.
摘要翻译：描述了用于恒定比特率有限缓冲大小视频编码器的速率控制的方法和装置。通过基于帧内的大小来调整非帧内的大小来提供速率控制。实施滑动窗口方法以避免位于一组图像结束附近的非帧内帧的过度调整。使用基于像素值的绝对值的和的“功率”的测量。 “功率”测量用于调整全局复杂度值，用于调整帧的大小。全局复杂度值响应场景变化。本发明的实施例计算并使用L 1距离和像素块复杂度来提供速率控制。本发明的一个实施例实现了多个比特预测器块。可以在图像级别，图像级别和像素块级别执行预测。当发生场景变化时，本发明的实施例重置全局复杂度参数。

9. 发明授权

US06978462B1 Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled 有权
标题翻译：对在匹配的事件的时间无关选择标准进行分析的执行间隔期间发生的事件序列的分析执行
公开(公告)号：US06978462B1
公开(公告)日：2005-12-20
申请号：US09332263
申请日：1999-06-11
申请人： Michael C. Adler , John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Stephen C. Purcell
发明人： Michael C. Adler , John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Stephen C. Purcell
IPC分类号： G06F3/00
CPC分类号： G06F11/348 , G06F9/30149 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3851
摘要： A computer having an instruction pipeline and profile circuitry. The profile circuitry detects and records, without compiler assistance for execution profiling, profile information describing a sequence of events occurring in the instruction pipeline. The sequence includes every event occurring during a profiled execution interval that matches time-independent selection criteria of events to be profiled. The recording continues until a predetermined stop condition is reached. The profile circuitry detects the occurrence of a predetermined condition, after a non-profiled interval of execution, and then commences the profiled execution interval.
摘要翻译：具有指令流水线和简档电路的计算机。简档电路检测和记录，无需编译器协助执行分析，描述描述在指令流水线中发生的事件序列的简档信息。该序列包括在分析执行间隔期间发生的每个事件，其与要分析的事件的时间无关的选择标准相匹配。记录继续，直到达到预定的停止条件。配置文件电路在非分析执行间隔之后检测预定条件的发生，然后开始分析执行间隔。

10. 发明授权

US06976265B1 Method and apparatus for controlling display of content signals 有权
标题翻译：用于控制内容信号显示的方法和装置
公开(公告)号：US06976265B1
公开(公告)日：2005-12-13
申请号：US09169023
申请日：1998-10-08
申请人： Ivan Yang , Stephen Orr , Andrew Morrison
发明人： Ivan Yang , Stephen Orr , Andrew Morrison
IPC分类号： H04N5/60 , H04N7/16 , H04N7/167
CPC分类号： H04N21/435 , H04N5/60 , H04N7/16 , H04N7/163 , H04N21/235 , H04N21/4318 , H04N21/439 , H04N21/4402 , H04N21/4532 , H04N21/454 , H04N21/84
摘要： A method and apparatus for controlling display of content signals begins by receiving a content signal that includes video content and at least one associated content control indicator. The content signal may also include audio content associated with the video content. The processing continues by comparing the at least one associated content control indicator (e.g., a rating of mature subject matter of the content signal) with at least one content control setting (e.g., a parental setting based on allowable viewing of rated content signals). When the associated content indicator compares unfavorably to the content control setting, a video graphics processor scrambles the at least a portion of the video content. The scrambled video content is then provided to a video rendering device for subsequent display.
摘要翻译：用于控制内容信号显示的方法和装置通过接收包括视频内容的内容信号和至少一个相关联的内容控制指示符开始。内容信号还可以包括与视频内容相关联的音频内容。该处理通过将至少一个相关联的内容控制指示符（例如，内容信号的成熟主题的评级）与至少一个内容控制设置（例如，基于额定内容信号的允许观看的父母设置）进行比较来继续。当相关联的内容指示符与内容控制设置不利地相比较时，视频图形处理器对视频内容的至少一部分进行加扰。然后将加扰的视频内容提供给视频呈现设备用于随后的显示。

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