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1. 发明授权

US09177645B2 10T NVSRAM cell and cell operations 有权
标题翻译： 10T NVSRAM单元和单元操作
公开(公告)号：US09177645B2
公开(公告)日：2015-11-03
申请号：US14058227
申请日：2013-10-19
申请人： Aplus Flash Technology, Inc
发明人： Hsing-Ya Tsao , Peter Wung Lee
IPC分类号： G11C14/00
CPC分类号： G11C14/0063
摘要： A 10T NVSRAM cell is provided with a bottom HV NMOS Select transistor in each 3T FString removed from traditional 12T NVSRAM cell. A Recall operation by reading a stored ΔVt state of flash transistors into each SRAM cell uses a charge-sensing scheme rather than the current-sensing scheme, with all other key operations unchanged. The Recall operation works under any ramping rate of SRAM's power line voltage and Flash gate signal which can be set higher than only Vt0 or both Vt0 and Vt1. Alternatively, the Store operation can use a current charging scheme from a Fpower line to the paired Q and QB nodes of each SRAM cell through a paired Flash Voltage Follower that stored ΔVtp≧1.0V. The Recall operation in this alternative embodiment is to use a 7-step approach with the FN-channel erase, FN-channel program and FN-edge program schemes, including 2-step SRAM amplification.
摘要翻译： 10T NVSRAM单元提供有从传统12T NVSRAM单元移除的每个3T FString中的底部HV NMOS选择晶体管。通过将闪存晶体管的存储的＆Dgr; Vt状态读入每个SRAM单元的回收操作使用电荷感测方案而不是电流感测方案，其他所有关键操作都不变。调用操作在SRAM的电源线电压和闪存栅极信号的任何斜坡率下工作，其可以被设置为高于仅Vt0或者Vt0和Vt1两者。或者，存储操作可以使用存储＆Dgr;Vtp≥1.0V的成对闪存电压跟随器从Fpower线路到每个SRAM单元的成对Q和QB节点的当前充电方案。该替代实施例中的调用操作是使用包括2步SRAM放大的FN通道擦除，FN通道程序和FN边缘程序方案的7步法。

2. 发明授权

US09087595B2 Shielding 2-cycle half-page read and program schemes for advanced NAND flash design 有权
标题翻译：屏蔽用于高级NAND闪存设计的2周期半页读取和编程方案
公开(公告)号：US09087595B2
公开(公告)日：2015-07-21
申请号：US13867051
申请日：2013-04-20
申请人： Aplus Flash Technology, Inc
发明人： Peter Wung Lee
IPC分类号： G11C16/26 , G11C16/04 , G11C11/56 , G11C16/24 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0408 , G11C16/0483 , G11C16/24 , G11C16/3427
摘要： The present invention provides a two-cycle half-page read scheme by dividing whole NAND array bit lines (BLs) into an odd-BL group and an even-BL group. During the half-plane reading of NAND cells in the odd(even)-BL group, the half-plane even(odd)-BL group acts as the shielding BLs to protect over the odd(even)-BL string reading so that each half-page read operation is substantially reliable and free from BL coupling noise effect. Additionally, each half-page read operation is preferably divided into 3 periods: the first being a bias-condition setup period of the selected WL and remaining control signals; the second being a pre-charge period for all BLs; and the third being a half-page flash data sensing period.
摘要翻译：本发明通过将整个NAND阵列位线（BL）分成奇数BL组和偶数BL组来提供双周期半页读取方案。在奇数（偶数）-BL组中的NAND单元的半平面读取期间，半平面偶数（奇数）-BL组用作屏蔽BL以在奇数（偶数）-BL字符串读数上保护，半页读取操作基本可靠，不受BL耦合噪声影响。此外，每个半页读取操作优选地被分为3个周期：第一个是所选WL的偏置条件建立周期和剩余的控制信号; 第二个是所有BL的预充电期; 第三个是半页闪存数据传感时段。

3. 发明授权

US08996785B2 NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface 有权
标题翻译：基于NAND的混合NVM设计，将NAND和NOR与1串口串行接口集成
公开(公告)号：US08996785B2
公开(公告)日：2015-03-31
申请号：US12807997
申请日：2010-09-17
申请人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G06F12/00 , G11C16/32 , G11C16/04
CPC分类号： G11C16/32 , G11C16/0408
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在串行接口上传输。串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码读取一个非易失性存储器阵列可能会中断读取另一个。一次读取操作具有两个子地址，一个命令之前传送一个。

4. 发明授权

US08971113B2 Pseudo-8T NVSRAM cell with a charge-follower 有权
标题翻译：带有充电跟随器的伪8T NVSRAM单元
公开(公告)号：US08971113B2
公开(公告)日：2015-03-03
申请号：US14064220
申请日：2013-10-28
申请人： Aplus Flash Technology, Inc
发明人： Peter Wung Lee
IPC分类号： G11C11/34 , G11C14/00
CPC分类号： G11C14/0063
摘要： The present invention discloses a 10T NVSRAM cell with a 6T SRAM cell with 4T Flash cell with one dedicated Flash-based Charger. In addition, a Pseudo-8T NVSRAM cell with a shared Flash-based Charger between two adjacent 8T NVSRAM cells at top and bottom in cell layout is also disclosed to further reduce cell size by 20%. As opposed to the prior art of 12T NVSRAM cell, the Store operation of the above two preferred embodiments use a DRAM-like charge-sensing scheme with Flash cell configured into a voltage follower ensured by the Flash-based Charger to obtain the final ΔVQ-QB>0.2V at Q and QB nodes of each SRAM cell to cover all the mismatched of parasitic capacitance in flash cell devices and layout for a reliable amplification by ramping up SRAM's VDD line and ramping down SRAM's VSS line.
摘要翻译：本发明公开了一种具有6T SRAM单元的10T NVSRAM单元，具有4T闪存单元和一个专用的基于闪存的充电器。此外，还公开了在单元格布局的顶部和底部的两个相邻的8T NVSRAM单元之间具有共享的基于闪存的充电器的伪8T NVSRAM单元，以进一步将单元大小减小20％。与12T NVSRAM单元的现有技术相反，上述两个优选实施例的存储操作使用具有闪存单元的DRAM状电荷感测方案，其被配置为由基于闪存的充电器确保的电压跟随器以获得最终的＆Dgr; 每个SRAM单元的Q和QB节点的VQ-QB> 0.2V，以覆盖闪存单元器件中的所有寄生电容失配，并通过升高SRAM的VDD线并降低SRAM的VSS线来布置可靠的放大。

5. 发明申请

US20140050025A1 LOW-VOLTAGE FAST-WRITE PMOS NVSRAM CELL 有权
标题翻译：低电压快速写入PMOS NVSRAM单元
公开(公告)号：US20140050025A1
公开(公告)日：2014-02-20
申请号：US13965031
申请日：2013-08-12
申请人： Hsing-Ya Tsao , Peter Wung Lee
发明人： Hsing-Ya Tsao , Peter Wung Lee
IPC分类号： G11C14/00
CPC分类号： G11C14/0063 , G11C14/00 , G11C16/04 , G11C16/0433 , G11C16/16
摘要： This invention discloses a low-voltage fast-write 12T or 14T PMOS NVSRAM cell structure which comprises a 6T LV SRAM cell and one pairs of two 3T or 4T HV PMOS Flash strings. Due to reverse threshold voltage definition of PMOS and NMOS flash cell, this PMOS NVSRAM cell has the advantage over the NMOS NVSRAM cell to have the same data polarity between SRAM and Flash pairs during the data writing operation. In addition, this PMOS NVSRAM's PMOS Flash cell uses similar low-current FN-tunneling scheme as NMOS NVSRAM, thus the fast data program and erase can be achieved in a big density up to 100 Mb simultaneously. As a result, low power voltage operation of NVSRAM with 1.2V VDD can be much easier to be designed without coupling the FSL line to any VDD level during the flash data loading into SRAM cell during a power-on period.
摘要翻译：本发明公开了一种低电压快写12T或14T PMOS NVSRAM单元结构，其包括6T LV SRAM单元和一对两个3T或4T HV PMOS闪存串。由于PMOS和NMOS闪存单元的反向阈值电压分辨率，该PMOS NVSRAM单元在数据写入操作期间具有超过NMOS NVSRAM单元在SRAM和闪存对之间具有相同数据极性的优势。此外，该PMOS NVSRAM的PMOS闪存单元使用与NMOS NVSRAM类似的低电流FN隧穿方案，因此快速数据编程和擦除可以同时实现高达100 Mb的大密度。因此，在上电期间闪存数据加载到SRAM单元期间，具有1.2V VDD的NVSRAM的低功耗电压操作可以轻松设计，无需将FSL线耦合到任何VDD电平。

6. 发明授权

US08634254B2 Single-polycrystalline silicon electrically erasable and programmable memory device of varied gate oxide thickness, using PIP or MIM coupling capacitor for cell size reduction and simultaneous VPP and VNN for write voltage reduction 失效
标题翻译：具有不同栅极氧化物厚度的单晶硅电可擦除可编程存储器件，使用PIP或MIM耦合电容器进行电池尺寸减小以及同时使用VPP和VNN进行写电压降低
公开(公告)号：US08634254B2
公开(公告)日：2014-01-21
申请号：US13052049
申请日：2011-03-19
申请人： Fu-Chang Hsu , Peter Wung Lee
发明人： Fu-Chang Hsu , Peter Wung Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/06
摘要： A single polycrystalline silicon floating gate nonvolatile memory device has a storage MOS transistor and at least one polycrystalline-insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor manufactured with dimensions that can be fabricated using current low voltage logic integrated circuit process. The PIP or MIM capacitor is a coupling capacitor with a first plate connected to a floating gate of the storage MOS transistor to form a floating gate node. The coupling PIP or MIM capacitor couples the voltage level applied to a second plate of the PIP or MIM capacitor to the floating gate node with a large coupling ratio approximately 90% so as to initiate Fowler-Nordheim tunneling effect for erasing or programming the memory device. The memory device may also have another PIP or MIM capacitor with a first plate connected to the floating gate of the storage MOS transistor for serving as a tunneling capacitor.
摘要翻译：单个多晶硅浮栅非易失性存储器件具有存储MOS晶体管和至少一个多晶绝缘体 - 多晶（PIP）或金属 - 绝缘体 - 金属（MIM）电容器，其制造尺寸可以使用当前的低电压逻辑集成电路处理。 PIP或MIM电容器是耦合电容器，其中第一板连接到存储MOS晶体管的浮置栅极，以形成浮动栅极节点。耦合PIP或MIM电容将施加到PIP或MIM电容器的第二板的电压电平耦合到具有大约90％的大耦合比的浮动栅极节点，以便启动用于擦除或编程存储器件的Fowler-Nordheim隧道效应。存储器件还可以具有另一个PIP或MIM电容器，其中第一板连接到用作隧道电容器的存储MOS晶体管的浮置栅极。

7. 发明授权

US08531885B2 NAND-based 2T2b NOR flash array with a diode connection to cell's source node for size reduction using the least number of metal layers 失效
标题翻译：基于NAND的2T2b NOR闪存阵列，使用二极管连接到电池的源节点，使用最少数量的金属层进行尺寸减小
公开(公告)号：US08531885B2
公开(公告)日：2013-09-10
申请号：US13116002
申请日：2011-05-26
申请人： Fu-Chang Hsu , Peter Wung Lee
发明人： Fu-Chang Hsu , Peter Wung Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C16/0483 , H01L27/1021 , H01L27/11524 , H01L29/872
摘要： A NAND-based NOR flash memory array has a matrix of NAND-based NOR flash cells arranged in rows and columns. Every two adjacent NAND-based NOR flash cells in a column share a common source node which is connected to a common source line through a diode. The source line may be made of a metal layer and is in contact directly with the source node or through an ohmic contact to form a Schottky barrier diode. The source line may also be made of a polysilicon or metal layer and connected to the source node through a pillar-structured polysilicon diode and a conduction layer. The diode may also be formed in the source node by enclosing a P/N+ junction diode in a heavily N+ doped region of the source node.
摘要翻译：基于NAND的NOR闪存阵列具有以行和列排列的基于NAND的NOR闪存单元的矩阵。列中每两个相邻的基于NAND的NOR闪存单元共享通过二极管连接到公共源极线的公共源节点。源极线可以由金属层制成并且与源节点直接接触或通过欧姆接触形成肖特基势垒二极管。源极线还可以由多晶硅或金属层制成并且通过柱结构的多晶硅二极管和导电层连接到源节点。二极管也可以通过在源节点的重N +掺杂区域中封装P / N +结二极管而形成在源节点中。

8. 发明申请

US20130215683A1 Three-Dimensional Flash-Based Combo Memory and Logic Design 审中-公开
标题翻译：三维闪存组合存储器和逻辑设计
公开(公告)号：US20130215683A1
公开(公告)日：2013-08-22
申请号：US13586451
申请日：2012-08-15
申请人： Peter Wung Lee , Hsing-Ya Tsao
发明人： Peter Wung Lee , Hsing-Ya Tsao
IPC分类号： G11C16/04 , H01L27/088
CPC分类号： G11C16/0466 , G11C11/5671 , H01L27/088 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L29/7926
摘要： A three-dimensional NAND-based NOR nonvolatile memory cell has two three-dimensional SONOS-type charge-retaining transistors arranged in a series string such that one of the charge-retaining transistors functions as a select gate transistor to prevent leakage current through the charge-retaining transistors when the charge-retaining transistors is not selected for determining a data state of the three-dimensional NAND-based NOR nonvolatile memory cell. The first charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the second charge retaining transistor's source is connected to a source line and is parallel to the bit line. The three-dimensional NAND-based NOR nonvolatile memory cell may be reconfigured to function as a PLD cell, an FPGA switching cell, and an EEPROM cell
摘要翻译：三维基于NAND的非易失性存储单元具有串联串联布置的两个三维SONOS型电荷保持晶体管，使得一个电荷保持晶体管用作选择栅极晶体管，以防止漏电流通过电荷当不选择电荷保持晶体管来确定三维基于NAND的非易失性存储单元的数据状态时，获得晶体管。第一电荷保持晶体管的漏极连接到与电荷保持晶体管平行的位线，并且第二电荷保持晶体管的源极连接到源极线并且平行于位线。可以将基于三维NAND的NOR非易失性存储单元重新配置为用作PLD单元，FPGA开关单元和EEPROM单元

9. 发明授权

US08472251B2 Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device 失效
标题翻译：单晶硅电可擦除和可编程非易失性存储器件
公开(公告)号：US08472251B2
公开(公告)日：2013-06-25
申请号：US12378036
申请日：2009-02-10
申请人： Peter Wung Lee , Fu-Chang Hsu
发明人： Peter Wung Lee , Fu-Chang Hsu
IPC分类号： G11C16/04 , G11C11/34 , H01L29/788 , H01L29/66
CPC分类号： H01L29/7883 , G11C16/0441 , G11C2216/10 , H01L27/11558 , H01L29/42324
摘要： A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. The physical size of the MOS capacitor is relatively large (approximately 10 time greater) when compared to a physical size of the storage MOS transistor to establish a large coupling ratio (greater than 80%) between the second plate of the MOS capacitor and the floating gate node. When a voltage is applied to the second plate of the MOS capacitor and a voltage applied to the source region or drain region of the MOS transistor establishes a voltage field within the gate oxide of the MOS transistor such that Fowler-Nordheim edge tunnel is initiated.
摘要翻译：单个多晶硅浮动非易失性存储单元具有MOS电容器和存储MOS晶体管，其制造尺寸允许使用电流低电压逻辑集成电路工艺制造。 MOS电容器具有连接到存储MOS晶体管的栅极的第一板，以形成浮栅节点。与存储MOS晶体管的物理尺寸相比，MOS电容器的物理尺寸相对较大（大约10倍），以在MOS电容器的第二板和浮置电容器之间建立大的耦合比（大于80％）门节点。当向MOS电容器的第二板施加电压，并且施加到MOS晶体管的源极区域或漏极区域的电压在MOS晶体管的栅极氧化物内建立电压场，从而启动Fowler-Nordheim边缘隧道。

10. 发明申请

US20130128667A1 Low-Voltage Page Buffer to be Used in NVM Design 有权
标题翻译：用于NVM设计的低电压页缓冲器
公开(公告)号：US20130128667A1
公开(公告)日：2013-05-23
申请号：US13680286
申请日：2012-11-19
申请人： Aplus Flash Technology, Inc.
发明人： Peter Wung Lee , Hsing-Ya Tsao
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/16
摘要： A low-current FN channel for Erase, Program, Program-Inhibit and Read operations is disclosed for any non-volatile memory using FN-tunneling scheme for program and erase operation, regardless NAND, NOR, and EEPROM and regardless PMOS or NMOS non-volatile cell type. As a result, all above NMV memories can use the disclosed LV, compact PGM buffer to replace the traditional HV PGM buffer for saving in the silicon area and power consumption. The page buffer is used to store new loaded data for new writing and to convert the stored data into the required BL HV voltage for either Erase or Program operations according to the stored data. In addition, the simpler on-chip State-machine design can be achieved with the superior quality of NVMs of this disclosure.
摘要翻译：公开了用于擦除，编程，程序禁止和读操作的低电流FN通道，用于使用用于编程和擦除操作的FN隧道方案的任何非易失性存储器，无论NAND，NOR和EEPROM，以及不管PMOS或NMOS非 - 挥发性细胞类型。因此，所有上述NMV存储器都可以使用所公开的LV，紧凑型PGM缓冲器来替代传统的HV PGM缓冲器，以节省硅面积和功耗。页面缓冲区用于存储用于新写入的新加载数据，并将存储的数据转换为所需的BL HV电压，以根据存储的数据进行擦除或编程操作。此外，可以通过本公开的NVM的优越品质来实现更简单的片上状态机设计。

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