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1. 再颁专利

USRE44218E1 Semiconductor memory device for controlling write recovery time 有权
标题翻译：用于控制写恢复时间的半导体存储器件
公开(公告)号：USRE44218E1
公开(公告)日：2013-05-14
申请号：US13335234
申请日：2011-12-22
申请人： Jae-Hyuk Im , Woon-Bok Lee
发明人： Jae-Hyuk Im , Woon-Bok Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C7/1045 , G11C7/1066 , G11C7/12 , G11C7/22 , G11C8/18 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/12015 , G11C29/50012
摘要： A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.
摘要翻译：一种半导体存储器件包括：CAS延迟模式检测装置，用于响应CAS延迟模式输出CAS等待时间控制信号; 以及自动预充电控制装置，用于响应于CAS等待时间控制信号来控制自动预充电操作的定时。

2. 发明授权

US08305833B2 Memory chip architecture having non-rectangular memory banks and method for arranging memory banks 有权
标题翻译：具有非矩形存储体的存储器芯片架构和用于排列存储体的方法
公开(公告)号：US08305833B2
公开(公告)日：2012-11-06
申请号：US11809244
申请日：2007-05-30
申请人： Jun-Hyun Chun
发明人： Jun-Hyun Chun
IPC分类号： G11C8/00
CPC分类号： G11C5/025 , G11C8/12 , G11C2207/105
摘要： A semiconductor memory device having semiconductor memory chips, each semiconductor memory chip includes a plurality of memory banks capable of independently to be accessed, each memory bank having a plurality of memory blocks, wherein at least two memory blocks, which are neighbored each other in the same memory bank, have the different number of unit memory blocks, so that each bank has a non-rectangular shape.
摘要翻译：一种具有半导体存储器芯片的半导体存储器件，每个半导体存储器芯片包括能够独立地被访问的多个存储器组，每个存储体具有多个存储器块，其中至少两个存储块彼此相邻相同的存储体，具有不同数量的单位存储块，使得每个存储体具有非矩形形状。

3. 再颁专利

USRE44532E1 Method for manufacturing a transistor of a semiconductor memory device 有权
标题翻译：半导体存储器件晶体管的制造方法
公开(公告)号：USRE44532E1
公开(公告)日：2013-10-08
申请号：US13586272
申请日：2012-08-15
申请人： Hyun Jung Kim
发明人： Hyun Jung Kim
IPC分类号： H01L29/82 , H01L43/00
CPC分类号： H01L29/7831 , H01L27/10823 , H01L27/10826 , H01L27/10844 , H01L29/7851
摘要： A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.
摘要翻译：一种半导体存储器件的晶体管，包括具有多个有源区和器件隔离区的半导体衬底，多个第一和第二沟槽器件隔离层，它们在半导体衬底的器件隔离区上相互交替布置所述第一沟槽器件隔离层具有对应于较高台阶高度的第一厚度，并且所述第二沟槽器件隔离层具有对应于相对较低台阶高度的第二厚度，在每个所述有源区域中形成的凹陷区域由预定深度在其边界部分处具有阶梯轮廓，所述凹陷区域的高度高于所述第二沟槽器件隔离层的高度，以在相邻的两个第二沟槽器件隔离层之间具有向上突出部分，栅极绝缘层和形成在栅极绝缘层上的与栅极堆叠重叠的多个栅极堆叠相应的活性区域的凸起轮廓和相关凹陷区域的突出部分。

4. 再颁专利

USRE44051E1 Data bus line control circuit 有权
公开(公告)号：USRE44051E1
公开(公告)日：2013-03-05
申请号：US13335207
申请日：2011-12-22
申请人： Tae Yun Kim
发明人： Tae Yun Kim
IPC分类号： G06F13/38 , G06F13/40
CPC分类号： G11C11/4097 , G11C11/4094
摘要： A data bus line control circuit prevents a problem of a data access operation on a global data bus (GDB) line although two blocks are simultaneously selected. The data bus line control circuit includes: a global data bus line which is arranged between memory units adjacent to each other as two pairs, and transmits a data from a local data bus line positioned between adjacent sub blocks; and transmission means which is connected between the local data bus line and the global data bus line, and transmits bit line signals of two sub blocks to one pair of global data bus lines different from each other through the local data bus line, when the two sub blocks are simultaneously selected by a block isolation selection signal. As a result, a circuit arrangement and a layout design become simplified, and two operations of 8K refresh and 4K refresh are possible in one chip, therefore, two kinds of effects can be achieved by one chip.

5. 发明授权

US08705312B2 Clock signal generation apparatus for use in semiconductor memory device and its method 有权
标题翻译：用于半导体存储器件的时钟信号产生装置及其方法
公开(公告)号：US08705312B2
公开(公告)日：2014-04-22
申请号：US13898998
申请日：2013-05-21
申请人： 658868 N.B. Inc.
发明人： Tae-Jin Kang
IPC分类号： G11C8/00
CPC分类号： G11C7/222 , G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.
摘要翻译：一种时钟信号产生装置，用于产生用于与来自半导体存储器件的外部时钟信号同步输出数据的参考时钟信号，包括：时钟信号产生单元，用于接收内部时钟信号以根据控制产生参考时钟信号信号; 以及用于基于读取命令，写入命令和外部地址产生控制信号的控制单元。

6. 发明申请

US20140098621A1 SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF 审中-公开
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20140098621A1
公开(公告)日：2014-04-10
申请号：US14100793
申请日：2013-12-09
申请人： 658868 N.B. Inc.
发明人： Young-Hoon OH , Kwang-Myoung RHO
IPC分类号： G11C11/4076
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1069 , G11C7/22 , G11C7/222 , G11C11/401 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.
摘要翻译：半导体存储器件包括：用于将延迟锁定环（DLL）时钟延迟预定延迟时间的可变延迟，以输出延迟的DLL时钟; 输出驱动器，用于响应于延迟的DLL时钟输出数据和数据选通信号; 以及校准控制器，用于响应于输出AC参数来控制可变延迟的预定延迟时间。

7. 再颁专利

USRE44590E1 Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption 有权
标题翻译：用于切换同步DRAM的内部时钟以降低功耗的时钟控制装置
公开(公告)号：USRE44590E1
公开(公告)日：2013-11-12
申请号：US13369988
申请日：2012-02-09
申请人： Chang-Ho Do
发明人： Chang-Ho Do
IPC分类号： G11C8/04 , G11C8/18
摘要： A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of flip-flops connected in series wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address, an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal, and a clock generator for generating the synchronous clock depending on the internal clock and the active signal.
摘要翻译：时钟控制装置包括用于响应于内部命令信号触发输入地址以输出第一地址的设置电路，包括串联连接的多个触发器的移位寄存器，其中一些触发器执行触发器，与内部时钟同步地提供第一地址以提供第二地址，并且剩余的触发器与同步时钟同步地顺序地执行第二地址的触发器操作以产生内部地址，有源信号发生器用于基于表示每个组是否被激活的活动控制信号的状态和预充电控制信号输出有效信号，以及用于根据内部时钟和有效信号产生同步时钟的时钟发生器。

8. 发明申请

US20140035042A1 METHOD FOR MANUFACTURING A TRANSISTOR OF A SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：用于制造半导体存储器件的晶体管的方法
公开(公告)号：US20140035042A1
公开(公告)日：2014-02-06
申请号：US14045419
申请日：2013-10-03
申请人： 658868 N.B. Inc.
发明人： Hyun Jung KIM
IPC分类号： H01L29/78
CPC分类号： H01L29/7831 , H01L27/10823 , H01L27/10826 , H01L27/10844 , H01L29/7851
摘要： A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.
摘要翻译：一种半导体存储器件的晶体管，包括具有多个有源区和器件隔离区的半导体衬底，多个第一和第二沟槽器件隔离层，它们在半导体衬底的器件隔离区上相互交替布置所述第一沟槽器件隔离层具有对应于较高台阶高度的第一厚度，并且所述第二沟槽器件隔离层具有对应于相对较低台阶高度的第二厚度，在每个所述有源区域中形成的凹陷区域由预定深度在其边界部分处具有阶梯轮廓，所述凹陷区域的高度高于所述第二沟槽器件隔离层的高度，以在相邻的两个第二沟槽器件隔离层之间具有向上突出部分，栅极绝缘层和形成在栅极绝缘层上的与栅极堆叠重叠的多个栅极堆叠相应的活性区域的凸起轮廓和相关凹陷区域的突出部分。

9. 发明申请

US20130242679A1 SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING WRITE RECOVERY TIME 有权
标题翻译：用于控制写入恢复时间的半导体存储器件
公开(公告)号：US20130242679A1
公开(公告)日：2013-09-19
申请号：US13892840
申请日：2013-05-13
申请人： 658868 N.B. INC.
发明人： Jae-Hyuk IM , Woon-Bok LEE
IPC分类号： G11C7/12
CPC分类号： G11C11/40615 , G11C7/1045 , G11C7/1066 , G11C7/12 , G11C7/22 , G11C8/18 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/12015 , G11C29/50012
摘要： A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.
摘要翻译：一种半导体存储器件包括：CAS延迟模式检测装置，用于响应CAS延迟模式输出CAS等待时间控制信号; 以及自动预充电控制装置，用于响应于CAS等待时间控制信号来控制自动预充电操作的定时。

10. 发明授权

US08357572B2 Method of manufacturing semiconductor device with recess and Fin structure 有权
标题翻译：具有凹槽和鳍结构的半导体器件的制造方法
公开(公告)号：US08357572B2
公开(公告)日：2013-01-22
申请号：US13360194
申请日：2012-01-27
申请人： Sang Don Lee , Sung Woong Chung
发明人： Sang Don Lee , Sung Woong Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L21/823437 , H01L29/4236 , H01L29/66621 , H01L29/7851
摘要： The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess.
摘要翻译：半导体器件包括有源区，凹槽，Fin沟道区，栅极绝缘膜和栅电极。有源区由半导体衬底中形成的器件隔离结构限定。通过使用岛状凹陷栅极掩模作为蚀刻掩模来蚀刻有源区及其邻近的器件隔离结构来形成凹部。鳍状沟道区在凹部的下部形成在半导体衬底上。栅极绝缘膜形成在包括鳍状沟道区域和凹部的有源区域上。栅电极形成在栅极绝缘膜上，以填充鳍沟道区域和凹槽。

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