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81. 发明授权

US09397689B2 Interpolator systems and methods 有权
标题翻译：内插系统和方法
公开(公告)号：US09397689B2
公开(公告)日：2016-07-19
申请号：US14551266
申请日：2014-11-24
申请人： Intel Corporation
发明人： Stefan Tertinek , Thomas Mayer , Peter Preyler
IPC分类号： H03M1/50 , H03M1/82 , H03M1/00 , H03M1/70 , H03M1/66
CPC分类号： H03M1/82 , H03K5/06 , H03K5/13 , H03K19/00361 , H03L7/0812 , H03M1/002 , H03M1/661 , H03M1/70
摘要： A digital to time converter is disclosed and includes a code logic and an interpolator. The code logic is configured to receive a first phase signal and a second phase signal and generate a select signal according to the first phase signal and the second phase signal. The interpolator has a bank of inverters. The interpolator is configured to generate an interpolator signal based on the select signal and an input signal.
摘要翻译：公开了数字到时间转换器，并且包括代码逻辑和内插器。代码逻辑被配置为接收第一相位信号和第二相位信号，并根据第一相位信号和第二相位信号产生选择信号。内插器有一组逆变器。内插器被配置为基于选择信号和输入信号产生内插器信号。

82. 发明授权

US09362934B2 Optically clocked digital/analog converter and a DDS unit with such a converter 有权
标题翻译：光学时钟数字/模拟转换器和带有这种转换器的DDS单元
公开(公告)号：US09362934B2
公开(公告)日：2016-06-07
申请号：US14397630
申请日：2013-04-24
申请人： Rohde & Schwarz GmbH & Co. KG
发明人： Gerhard Kahmen
IPC分类号： H03M1/66 , H03M1/08 , H03M1/72 , G02F7/00 , H03M1/70 , H03M1/74
CPC分类号： H03M1/0836 , G02F7/00 , H03M1/66 , H03M1/70 , H03M1/72 , H03M1/745
摘要： A digital/analog converter (30) with a first return-to-zero unit (311) which is connected to a first busbar (321), wherein the first busbar (321) is connected in each case to a first output of several differential units (351, 352, 35n). In this context, the first return-to-zero unit (311) provides at least one clock input which is directly or indirectly connected to a first photodiode, wherein the first photodiode is fed from a pulsed light source (5).
摘要翻译：具有连接到第一母线（321）的第一归零单元（311）的数字/模拟转换器（30），其中第一母线（321）在每种情况下都连接到多个差分的第一输出端单位（351,352,35n）。在这种情况下，第一归零单元（311）提供至少一个时钟输入，其直接或间接连接到第一光电二极管，其中第一光电二极管从脉冲光源（5）馈送。

83. 发明授权

US09287888B2 Converter with an additional DC offset and method thereof 有权
标题翻译：具有附加DC偏移的转换器及其方法
公开(公告)号：US09287888B2
公开(公告)日：2016-03-15
申请号：US14588816
申请日：2015-01-02
申请人： Realtek Semiconductor Corp.
发明人： Ming-Cheng Chiang , Wei-Cheng Tang
IPC分类号： H03M1/06 , H03M1/08 , H03M1/18 , H03M1/70
CPC分类号： H03M1/0845 , H03M1/183 , H03M1/70 , H03M3/356 , H03M3/422 , H03M3/458 , H03M3/50
摘要： A converter with an additional DC offset includes a switch circuit, a first capacitor, a plurality of additional capacitor cells and an operational amplifier. The converter uses a first additional capacitor cell and a second additional capacitor cell having a capacitor difference with the first additional capacitor to store two charges having different polarity and magnitude with each other, and further generate an inverted DC offset according to a difference between the two charges to compensate a DC offset.
摘要翻译：具有附加DC偏移的A转换器包括开关电路，第一电容器，多个附加电容器单元和运算放大器。转换器使用第一附加电容器单元和具有与第一附加电容器的电容器差异的第二附加电容器单元来存储彼此具有不同极性和大小的两个电荷，并且还根据两者之间的差异产生反相DC偏移充电以补偿DC偏移。

84. 发明申请

US20160049948A1 MULTI-ZONE DATA CONVERTERS 有权
公开(公告)号：US20160049948A1
公开(公告)日：2016-02-18
申请号：US14925040
申请日：2015-10-28
申请人： MaxLinear, Inc.
发明人： Curtis Ling
IPC分类号： H03M1/00 , H04B1/40 , H03M1/70 , H03M1/74 , H03M1/18 , H03M1/36
CPC分类号： H03M1/002 , H03M1/12 , H03M1/188 , H03M1/36 , H03M1/66 , H03M1/70 , H03M1/74 , H04B1/40
摘要： Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

85. 发明授权

US09154154B2 Method and system for a low input voltage low impedance termination stage for current inputs 有权
标题翻译：用于电流输入的低输入电压低阻抗终端级的方法和系统
公开(公告)号：US09154154B2
公开(公告)日：2015-10-06
申请号：US14471587
申请日：2014-08-28
申请人： Maxlinear, Inc.
发明人： Rajesh Zele , Gaurav Chandra
IPC分类号： H03M1/66 , H03M1/70
CPC分类号： H03M1/66 , H03F3/45192 , H03F2203/45526 , H03M1/70 , H03M1/742
摘要： Methods and systems for a low input voltage low impedance termination stage for current inputs may include, in a semiconductor die, generating an output current proportional to an input signal, where the output current is generated by an output stage that may include a pair of input cascode transistors and at least one pair of stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source that is coupled to ground. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor.
摘要翻译：用于电流输入的低输入电压低阻抗终端级的方法和系统可以包括在半导体管芯中产生与输入信号成比例的输出电流，其中输出电流由输出级产生，输出级可包括一对输入共源共栅晶体管和至少一对堆叠输出晶体管。用于输入共源共栅晶体管的源极 - 跟随器反馈路径可以包括其栅极端子耦合到输入共源共栅晶体管中的第一个的漏极端子的反馈晶体管，耦合到电源电压的反馈晶体管的漏极和源极端子耦合到耦合到地的电流源的反馈晶体管。电流源可以耦合到第一输入共源共栅晶体管的漏极。电源电压可以经由负载电阻器耦合到堆叠的输出晶体管。

86. 发明授权

US09154153B2 Offset compensation in driving circuits 有权
标题翻译：驱动电路偏移补偿
公开(公告)号：US09154153B2
公开(公告)日：2015-10-06
申请号：US14397936
申请日：2012-05-04
申请人： Michael J. Conroy , Miroslaw Marek Grotkowski
发明人： Michael J. Conroy , Miroslaw Marek Grotkowski
IPC分类号： G05F1/00 , H05B37/02 , H05B41/36 , H05B39/04 , H03M1/70 , G05F1/56 , H02M3/156 , H05B33/08
CPC分类号： H03M1/70 , G05F1/56 , H02M3/156 , H05B33/0815 , Y10T307/406
摘要： Apparatus and methods are presented for compensating for offsets in digital-to-analog converters (DACs). An apparatus may comprise a gain block. The non-inverting input of the gain block may be provided with a bias voltage selected to exceed the worst-case expected positive offset of a DAC. Feedback from the output of the gain block may be provided to a processor. The processor may be connected to drive the DAC.
摘要翻译：提出了用于补偿数模转换器（DAC）中的偏移的装置和方法。装置可以包括增益块。增益块的非反相输入可以被提供有被选择为超过DAC的最坏情况期望的正偏移的偏置电压。来自增益块的输出的反馈可以被提供给处理器。处理器可能被连接以驱动DAC。

87. 发明申请

US20150214969A1 MULTIPLYING DIGITAL-TO-ANALOG CONVERTER AND PIPELINE ANALOG-TO-DIGITAL CONVERTER USING THE SAME 有权
标题翻译：使用数字模拟转换器和管道模拟数字转换器
公开(公告)号：US20150214969A1
公开(公告)日：2015-07-30
申请号：US14508234
申请日：2014-10-07
申请人： MediaTek Inc.
发明人： Yuan-Ching LIEN
IPC分类号： H03M1/00 , H03M1/72 , H03M1/46 , H03M1/70 , H03M1/06 , H03M1/18
CPC分类号： H03M1/002 , H03M1/468
摘要： A multiplying digital-to-analog converter (MDAC) with high slew rate and a pipeline Analog-to-digital converter using the same. The first set of capacitors for a first input terminal of the operational amplifier (op-amp) includes active capacitors coupling the first input terminal of the op-amp to a first enhanced reference voltage or a common mode terminal in accordance with first digital bits in an amplifying phase of the MDAC, and includes a feedback capacitor coupling the first input terminal of the op-amp to a first output terminal of the op-amp in the amplifying phase. The first set of capacitors contains M capacitor cells. The feedback capacitor between the first set of capacitors contains at most M/(2n) capacitor cells, where n is a number of effective bits provided by a first analog-to-digital converter generating the first digital bits for the active capacitors.
摘要翻译：具有高压摆率的倍增数模转换器（MDAC）和使用该数模转换器的管线模数转换器。用于运算放大器（运算放大器）的第一输入端的第一组电容器包括有源电容器，其根据第一数字位将运算放大器的第一输入端耦合到第一增强参考电压或共模终端 MDAC的放大相位，并且包括将放大器的运算放大器的第一输入端子耦合到运算放大器的第一输出端子的反馈电容器。第一组电容器包含M个电容器单元。第一组电容器之间的反馈电容器包含至多M /（2n）个电容器单元，其中n是由有源电容器产生第一数字位的第一模数转换器提供的有效位数。

88. 发明申请

US20150194949A1 TEMPERATURE-COMPENSATED HIGH ACCURACY CLOCK 有权
标题翻译：温度补偿高精度时钟
公开(公告)号：US20150194949A1
公开(公告)日：2015-07-09
申请号：US14149219
申请日：2014-01-07
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： DALE J. MCQUIRK , Michael T. Berens
IPC分类号： H03K3/011 , H03K5/00 , H03M1/70
CPC分类号： H03K3/011 , H03K5/00006 , H03M1/785 , H03M1/808
摘要： A tunable clock circuit has a dual overlapping digital to analog converter (DAC) and an oscillator. The dual overlapping DAC provides a first output selectable with a first resolution and a second output selectable with a second resolution. The first resolution is different from the second resolution. The oscillator has a first input coupled to the first output of the dual overlapping DAC, a second input coupled to the second output of the dual overlapping DAC, and an output providing a clock output signal.
摘要翻译：可调谐时钟电路具有双重重叠的数模转换器（DAC）和振荡器。双重重叠DAC提供可选择的第一输出，具有第一分辨率，第二输出可选择具有第二分辨率。第一项决议与第二项决议有所不同。振荡器具有耦合到双重重叠DAC的第一输出的第一输入，耦合到双重叠DAC的第二输出的第二输入和提供时钟输出信号的输出。

89. 发明授权

US09054660B1 Amplifying system 有权
标题翻译：放大系统
公开(公告)号：US09054660B1
公开(公告)日：2015-06-09
申请号：US14152515
申请日：2014-01-10
申请人： Kirubakaran Ramalingam , Rabeesh Vadassery Gopinathan , Kaushal Kumar Jha , Damien J. McCartney
发明人： Kirubakaran Ramalingam , Rabeesh Vadassery Gopinathan , Kaushal Kumar Jha , Damien J. McCartney
IPC分类号： H03F1/48 , H03F3/45 , H03G3/00 , H03M1/66 , H03M1/70 , H03G3/30
CPC分类号： H03G3/001 , H03G1/0088
摘要： A digital-to-analog conversion system includes a digital-to-analog converter and an output stage for converting an output signal of the digital-to-analog converter into a voltage range. The output stage includes a first amplifier including a first input for receiving the output signal of the digital-to-analog converter, a first resistance element coupled between a second input and an output of the first amplifier, a second resistance element coupled between the second input of the first amplifier and a ground reference, and a third resistance element switchably coupled from the second input of the first amplifier to an offset voltage.
摘要翻译：数模转换系统包括数模转换器和用于将数模转换器的输出信号转换成电压范围的输出级。输出级包括第一放大器，其包括用于接收数模转换器的输出信号的第一输入端，耦合在第一放大器的第二输入端和第二输出端之间的第一电阻元件，第一放大器的输入和接地基准，以及从第一放大器的第二输入端切换耦合到偏移电压的第三电阻元件。

90. 发明申请

US20050219092A1 DAC DC OFFSET CALIBRATION METHOD AND RELATED APPARATUS 失效
标题翻译： DAC直流偏移校准方法及相关装置
公开(公告)号：US20050219092A1
公开(公告)日：2005-10-06
申请号：US10906543
申请日：2005-02-24
申请人： Chia-Yi Chang , Yeou-Jyh Tsai
发明人： Chia-Yi Chang , Yeou-Jyh Tsai
IPC分类号： H03M1/06 , H03M1/10 , H03M1/66 , H03M1/70
CPC分类号： H03M1/1023 , H03M1/1014 , H03M1/66
摘要： The present invention discloses a DAC DC offset calibration method and related apparatus. The disclosed method includes the following steps. First, apply a first value and a second value to the DAC to generate a first measurement value and a second measurement value respectively. Then, without using any predetermined parameter, determine a DC compensation value according to the first value, the second value, the first measurement value, and the second measurement value. The DC compensation value is used to calibrate the DAC.
摘要翻译：本发明公开了一种DAC直流偏移校准方法及相关装置。所公开的方法包括以下步骤。首先，将第一值和第二值应用于DAC以分别产生第一测量值和第二测量值。然后，在不使用任何预定参数的情况下，根据第一值，第二值，第一测量值和第二测量值来确定DC补偿值。 DC补偿值用于校准DAC。

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