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81. 发明申请

US20110109422A1 Impedance Calibration Circuit with Uniform Step Heights 有权
标题翻译：具有均匀步距的阻抗校准电路
公开(公告)号：US20110109422A1
公开(公告)日：2011-05-12
申请号：US12859920
申请日：2010-08-20
申请人： Ying-Yu Hsu
发明人： Ying-Yu Hsu
IPC分类号： H01C13/00
CPC分类号： H01C13/00 , H01C10/50 , H03H7/40 , H03H11/30 , H03K17/163 , H04L25/0278
摘要： An integrated circuit includes a first connection line; a second connection line; a plurality of tuning resistors with each having a sequence number and being coupled between the first connection line and the second connection line; and a plurality of switches, with each being coupled in series with one of the plurality of tuning resistors. The sequence numbers of the plurality of tuning resistors are continuous. The resistance values of the plurality of tuning resistors are a function of the respective sequence numbers.
摘要翻译：集成电路包括第一连接线; 第二连接线; 多个调谐电阻器，每个具有序列号并且耦合在所述第一连接线和所述第二连接线之间; 以及多个开关，每个开关与多个调谐电阻器中的一个串联耦合。多个调谐电阻器的序列号是连续的。多个调谐电阻器的电阻值是各序列号的函数。

82. 发明授权

US07940101B2 Slew rate control for a load switch 失效
标题翻译：负载开关的转换速率控制
公开(公告)号：US07940101B2
公开(公告)日：2011-05-10
申请号：US12199890
申请日：2008-08-28
申请人： Abhay Kumar Rai , Ronald Dean Gillingham
发明人： Abhay Kumar Rai , Ronald Dean Gillingham
IPC分类号： H03K5/12
CPC分类号： H03K5/05 , H03K17/163 , H03K17/164
摘要： An apparatus for slew rate control using a plurality of discrete slew rate levels. The apparatus includes a load switch and a switch controller. The load switch outputs a load voltage to a load. The switch controller generates a switch control signal in response to an enable signal. The switch control signal controls operation of the load switch. The switch controller controls a slew rate of the load switch according to a plurality of discrete slew rate levels.
摘要翻译：一种使用多个离散转换速率水平的转换速率控制的装置。该装置包括负载开关和开关控制器。负载开关向负载输出负载电压。开关控制器响应于使能信号产生开关控制信号。开关控制信号控制负载开关的动作。开关控制器根据多个离散转换速率水平控制负载开关的转换速率。

83. 发明授权

US07859315B2 Driver circuit 有权
标题翻译：驱动电路
公开(公告)号：US07859315B2
公开(公告)日：2010-12-28
申请号：US12330110
申请日：2008-12-08
申请人： Akira Nakamori , Takahiro Mori , Tomoyuki Yamazaki
发明人： Akira Nakamori , Takahiro Mori , Tomoyuki Yamazaki
IPC分类号： H03B1/00
CPC分类号： H03K17/168 , H03K17/163 , H03K2217/0036
摘要： A driver circuit facilitates reducing noises and losses and improving the driving performances thereof without connecting a series circuit of capacitor and a resistor to the gate of IGBT. The driver circuit includes a slope setting circuit that sets the gate voltage waveform of IGBT; and an operational amplifier that includes a non-inverting input terminal, to which an output voltage V* from slope setting circuit is inputted, and an inverting input terminal, to which a divided voltage Vgsf divided by resistors is inputted; and the operational amplifier outputs an output voltage Vout, proportional to the difference between the output voltage V* and the divided voltage Vgsf, to the gate of IGBT.
摘要翻译：驱动电路有助于降低噪声和损耗，并提高其驱动性能，而无需将电容器和电阻器的串联电路连接到IGBT的栅极。驱动电路包括设置IGBT栅极电压波形的斜坡设定电路; 以及运算放大器，其包括输入来自斜坡设定电路的输出电压V *的非反相输入端子和输入了由电阻器分压的分压电压Vgsf的反相输入端子; 并且运算放大器将与输出电压V *和分压Vgsf之间的差成比例的输出电压Vout输出到IGBT的栅极。

84. 发明授权

US07852111B2 Semiconductor device and impedance adjustment method of the same 有权
标题翻译：半导体器件和阻抗调节方法相同
公开(公告)号：US07852111B2
公开(公告)日：2010-12-14
申请号：US12409838
申请日：2009-03-24
申请人： Takashi Oguri
发明人： Takashi Oguri
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K17/163 , H03K19/017581
摘要： A 4-bit counter outputs a 4-bit counted value CNTp based on an up-and-down signal Sp supplied from a comparator. A weighting selection circuit performs weighting based on a deviation from an average value of the DC characteristic of each PMOS transistor, and assigns a transistor having the smallest deviation to Bit 1 (LSB) of the 4-bit counter. The weighting selection circuit assigns two PMOS transistors to Bit 2 of the 4-bit counter, four PMOS transistors to Bit 3, and eight PMOS transistors to Bit 4 (MSB). Then, the weighting selection circuit selects transistors P3-1 to P3-30 based on the counted value CNTp output from the 4-bit counter.
摘要翻译： 4位计数器基于从比较器提供的上下降信号Sp输出4位计数值CNTp。加权选择电路根据与每个PMOS晶体管的DC特性的平均值的偏差进行加权，并将具有最小偏差的晶体管分配给4位计数器的位1（LSB）。加权选择电路将两个PMOS晶体管分配给4位计数器的位2，将4个PMOS晶体管分配给位3，将8个PMOS晶体管分配到位4（MSB）。然后，加权选择电路基于从4位计数器输出的计数值CNTp选择晶体管P3-1至P3-30。

85. 再颁专利

USRE41926E1 Output circuit for adjusting output voltage slew rate 有权
标题翻译：用于调节输出电压转换速率的输出电路
公开(公告)号：USRE41926E1
公开(公告)日：2010-11-16
申请号：US11223913
申请日：2005-09-09
申请人： An-Ming Lee
发明人： An-Ming Lee
IPC分类号： H03K5/12
CPC分类号： H03K17/163 , H03K19/00361
摘要： The present invention discloses an output circuit that is able to adjust the output voltage slew rate and avoid short-circuit current, comprising: a control circuit for receiving an input data and generating a first set of control signals based on the input data; an output control device consisting of a first field effect transistor (FET) connected in series with a second field effect transistor (FET) and the point of connection is the output end for generating an output signal; a first capacitor having one end connected to a first working voltage and generates a first control voltage by charging/discharging on another end to control the gate of the first field effect transistor; a first switch for controlling charging/discharging of the first capacitor device based on the first set of control signals; a first current source for providing charging current for the first capacitor device; a second capacitor having one end connected to a second working voltage and generates a second control voltage by charging/discharging on another end to control the gate of the second field effect transistor; a second switch for controlling charging/discharging of the second capacitor device based on the first set of control signal; and a second current source providing charging current for the second capacitor device. The present invention adjusts output voltage slew rate of the output circuit by adjusting the time constant of the first and second capacitor devices.
摘要翻译：本发明公开了一种能够调节输出电压转换速率并避免短路电流的输出电路，包括：控制电路，用于接收输入数据并基于输入数据产生第一组控制信号; 由与第二场效应晶体管（FET）串联连接的第一场效应晶体管（FET）和连接点组成的输出控制装置是用于产生输出信号的输出端; 第一电容器，其一端连接到第一工作电压，并通过在另一端充电/放电来产生第一控制电压，以控制第一场效应晶体管的栅极; 用于基于所述第一组控制信号控制所述第一电容器装置的充电/放电的第一开关; 用于为第一电容器装置提供充电电流的第一电流源; 第二电容器，其一端连接到第二工作电压，并通过在另一端充电/放电来产生第二控制电压，以控制第二场效应晶体管的栅极; 用于基于所述第一组控制信号控制所述第二电容器装置的充电/放电的第二开关; 以及为第二电容器装置提供充电电流的第二电流源。本发明通过调整第一和第二电容器装置的时间常数来调节输出电路的输出电压转换速率。

86. 发明申请

US20100237911A1 Drive Circuit For A Power Switch Component 有权
标题翻译：电源开关元件驱动电路
公开(公告)号：US20100237911A1
公开(公告)日：2010-09-23
申请号：US12681660
申请日：2007-10-05
申请人： Andreas Svensson
发明人： Andreas Svensson
IPC分类号： H03K3/02
CPC分类号： H03K17/6872 , H03K17/163 , H03K17/284
摘要： A drive circuit for a power switch component.
摘要翻译：电源开关元件的驱动电路。

87. 发明授权

US07786753B2 Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device 有权
标题翻译：输出驱动器电路，包括输出驱动电路的半导体存储器件以及用于操作半导体存储器件的方法
公开(公告)号：US07786753B2
公开(公告)日：2010-08-31
申请号：US12165101
申请日：2008-06-30
申请人： Chun-Seok Jeong , Kee-Teok Park
发明人： Chun-Seok Jeong , Kee-Teok Park
IPC分类号： H03K19/003
CPC分类号： H03K19/00361 , H03K17/163 , H03K19/018585
摘要： Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up control signal and a pull-down control signal according to a logic value of data to output, and to adjust and output a slew rate of the pull-up control signal and a slew rate of the pull-down control signal according to a termination resistance setting information, a pull-up driver to output logic high data in response to the pull-up control signal and a pull-down driver to output logic low data in response to the pull-down control signal.
摘要翻译：输出驱动器电路，包括输出驱动器电路的半导体存储器件和用于操作半导体存储器件的方法，包括预驱动器，以根据数据的逻辑值产生上拉控制信号和下拉控制信号输出，并且根据终端电阻设置信息调整和输出上拉控制信号的转换速率和下拉控制信号的转换速率，上拉驱动器响应于输出逻辑高数据而输出逻辑高数据上拉控制信号和下拉驱动器，以响应于下拉控制信号输出逻辑低数据。

88. 发明授权

US07449913B1 Pre-driver having slew-rate and crowbar-current controls for a CMOS output buffer 有权
标题翻译：预驱动器具有CMOS输出缓冲器的转换速率和短路电流控制
公开(公告)号：US07449913B1
公开(公告)日：2008-11-11
申请号：US11765751
申请日：2007-06-20
申请人： Kenneth Wai Ming Hung
发明人： Kenneth Wai Ming Hung
IPC分类号： H03K17/16 , H03B1/00
CPC分类号： H03K17/6872 , H03K17/163
摘要： An output buffer having slew-rate control and crossbar current control includes a pull-up PMOS transistor, a pull-down NMOS transistor, a pull-up network coupled to the gate of the pull-up PMOS transistor, and a pull-down network coupled to the gate of the pull-down NMOS transistor.
摘要翻译：具有压摆率控制和横向电流控制的输出缓冲器包括上拉PMOS晶体管，下拉式NMOS晶体管，耦合到上拉PMOS晶体管的栅极的上拉网络以及下拉网络耦合到下拉式NMOS晶体管的栅极。

89. 发明申请

US20080238213A1 SWITCHING CIRCUIT, SIGNAL OUTPUT DEVICE AND TEST APPARATUS 审中-公开
标题翻译：开关电路，信号输出装置和测试装置
公开(公告)号：US20080238213A1
公开(公告)日：2008-10-02
申请号：US11766799
申请日：2007-06-22
申请人： Seiji AMANUMA
发明人： Seiji AMANUMA
IPC分类号： H03K17/00
CPC分类号： H03K17/0412 , H03K17/04123 , H03K17/163 , H03K17/28 , H03K17/284 , H03K17/6871 , H03K17/6877 , Y10T307/747 , Y10T307/76 , Y10T307/964
摘要： There is provided a switching circuit that opens or short-circuits between a first terminal and a second terminal in accordance with a control signal. The switching circuit includes a plurality of switching devices that is serially connected between the first terminal and the second terminal and each of which is opened or short-circuited in accordance with a provided control voltage, and a plurality of control circuits that is provided one-to-one corresponding to the plurality of switching devices, each of which provides a control voltage according to the control signal to the corresponding switching device, and that opens and short-circuits the plurality of switching devices in synchronization with each other.
摘要翻译：提供了根据控制信号在第一端子和第二端子之间断开或短路的开关电路。开关电路包括串联连接在第一端子和第二端子之间的多个开关装置，其中每个开关装置根据所提供的控制电压而断开或短路;以及多个控制电路，一对应于多个开关装置，每个开关装置根据控制信号向相应的开关装置提供控制电压，并且使多个开关装置彼此同步地打开和短路。

90. 发明申请

US20080212247A1 Insulated gate bipolar transistor fault protection system 有权
标题翻译：绝缘栅双极晶体管故障保护系统
公开(公告)号：US20080212247A1
公开(公告)日：2008-09-04
申请号：US11986615
申请日：2007-11-21
申请人： Jun-Bae Lee , Dae-Woong Chung , Bum-Seok Suh
发明人： Jun-Bae Lee , Dae-Woong Chung , Bum-Seok Suh
IPC分类号： H02H3/02
CPC分类号： H03K17/08128 , H03K17/163 , H03K17/567 , H03K2217/0027
摘要： An Insulated Gate Bipolar Transistor (IGBT) fault protection system is provided. The fault protection system includes a GVPA, a gate voltage clamper, and a soft-off unit. The GVPA analyzes a gate voltage pattern of an IGBT to determine whether or not a fault has occurred. The gate voltage clamper prevents an increase in a gate voltage of the IGBT according to an output signal that the GVPA outputs when a fault has occurred. The soft-off unit softly turns off the IGBT according to an output signal that the GVPA outputs when a fault has occurred.
摘要翻译：提供绝缘栅双极晶体管（IGBT）故障保护系统。故障保护系统包括GVPA，栅极电压钳位器和软关断单元。 GVPA分析IGBT的栅极电压模式，以确定是否发生故障。栅极电压钳位器根据在发生故障时GVPA输出的输出信号防止IGBT栅极电压的增加。软断开单元根据发生故障时GVPA输出的输出信号轻轻地关闭IGBT。

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