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81. 发明授权

US09478630B2 Fully isolated LIGBT and methods for forming the same 有权
标题翻译：完全隔离的LIGBT及其形成方法
公开(公告)号：US09478630B2
公开(公告)日：2016-10-25
申请号：US14559674
申请日：2014-12-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
IPC分类号： H01L29/66 , H01L21/70 , H01L21/332 , H01L29/739 , H01L29/06 , H01L21/761 , H01L21/762 , H01L21/265 , H01L21/304 , H01L21/76
CPC分类号： H01L29/66325 , H01L21/265 , H01L21/304 , H01L21/76 , H01L21/761 , H01L21/76224 , H01L29/0696 , H01L29/7393 , H01L29/7394
摘要： A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.
摘要翻译：一种器件包括电介质层和介电层上的重掺杂半导体层。重掺杂半导体层是第一导电类型。半导体区域在重掺杂半导体层之上，其中半导体区域是与第一导电类型相反的第二导电类型。横向绝缘栅双极晶体管（LIGBT）设置在半导体区域的表面。

82. 发明申请

US20160260824A1 Bipolar Semiconductor Device Having a Charge-Balanced Inter-Trench Structure 有权
标题翻译：具有电荷平衡的沟槽间结构的双极半导体器件
公开(公告)号：US20160260824A1
公开(公告)日：2016-09-08
申请号：US14986150
申请日：2015-12-31
申请人： Florin Udrea , Alice Pei-Shan Hsieh , Gianluca Camuso , Chiu Ng , Yi Tang , Rajeev Krishna Vytla
发明人： Florin Udrea , Alice Pei-Shan Hsieh , Gianluca Camuso , Chiu Ng , Yi Tang , Rajeev Krishna Vytla
IPC分类号： H01L29/739 , H01L29/10 , H01L29/06
CPC分类号： H01L29/7397 , H01L29/0634 , H01L29/41708 , H01L29/7394
摘要： There are disclosed herein various implementations of a bipolar semiconductor device having a charge-balanced inter-trench structure. Such a device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type. The device also includes first and second control trenches extending through an inversion region having the second conductivity type into the drift region, each of the first and second control trenches being bordered by a cathode diffusion having the first conductivity type. In addition, the device includes an inter-trench structure situated in the drift region between the first and second control trenches. The inter-trench structure includes one or more first conductivity regions having the first conductivity type and one or more second conductivity region having the second conductivity type, the one or more first conductivity regions and the one or more second conductivity regions configured to substantially charge-balance the inter-trench structure.
摘要翻译：这里公开了具有电荷平衡的沟槽间结构的双极半导体器件的各种实施方式。这种器件包括位于具有第二导电类型的阳极层上的具有第一导电类型的漂移区。该器件还包括延伸穿过具有第二导电类型的反向区域到漂移区域中的第一和第二控制沟槽，第一和第二控制沟槽中的每一个都由具有第一导电类型的阴极扩散区界定。此外，该器件包括位于第一和第二控制沟槽之间的漂移区域中的沟槽间结构。沟槽间结构包括具有第一导电类型的一个或多个第一导电区域和具有第二导电类型的一个或多个第二导电区域，一个或多个第一导电区域和一个或多个第二导电区域，平衡沟槽间结构。

83. 发明授权

US09240469B2 Transverse ultra-thin insulated gate bipolar transistor having high current density 有权
标题翻译：具有高电流密度的横向超薄绝缘栅双极晶体管
公开(公告)号：US09240469B2
公开(公告)日：2016-01-19
申请号：US14439715
申请日：2012-12-27
申请人： SOUTHEAST UNIVERSITY
发明人： Weifeng Sun , Jing Zhu , Shen Xu , Qinsong Qian , Siyang Liu , Shengli Lu , Longxing Shi
IPC分类号： H01L29/66 , H01L29/739 , H01L29/06 , H01L29/49 , H01L29/10 , H01L29/08 , H01L23/528
CPC分类号： H01L29/7394 , H01L23/528 , H01L29/0611 , H01L29/0696 , H01L29/0808 , H01L29/0821 , H01L29/0847 , H01L29/1008 , H01L29/4916 , H01L2924/0002 , H01L2924/00
摘要： A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.
摘要翻译：具有电流密度的横向超薄绝缘栅双极晶体管包括：P基板，其中P基板在其上设置有掩埋氧化物层，所述掩埋氧化物层在其上设置有N外延层，提供N外延层在其中具有N阱区域和P基极区域，P基极区域中设置有第一P接触区域和N源极区域，N阱区域中设置有N个缓冲区域，N阱区域设置有在其上的场氧化物层，N缓冲区在其中设置有P漏极区，N外延层中设置有包括P环状基极区的P基区阵列，P基区阵列位于N阱之间区域和P基区域中，P环状基部区域设置有第二P接触区域和N环状源极区域，第二P接触区域位于N环状源极区域中。本发明大大增加了横向超薄绝缘栅双极晶体管的电流密度，从而显着提高了智能功率模块的性能。

84. 发明申请

US20150303288A1 Switching Device for Power Conversion and Power Conversion Device 有权
标题翻译：电源转换和电源转换装置的开关装置
公开(公告)号：US20150303288A1
公开(公告)日：2015-10-22
申请号：US14418610
申请日：2012-09-07
申请人： Takayuki HASHIMOTO , Mutsuhiro MORI , Masahiro MASUNAGA
发明人： Takayuki HASHIMOTO , Mutsuhiro MORI , Masahiro MASUNAGA
IPC分类号： H01L29/739 , H02M7/537
CPC分类号： H02M1/088 , H01L29/0619 , H01L29/0696 , H01L29/0804 , H01L29/0821 , H01L29/1079 , H01L29/41708 , H01L29/4236 , H01L29/4238 , H01L29/7394 , H01L29/7396 , H01L29/7397 , H02M1/08 , H02M7/003 , H02M7/537 , H02M7/5387 , H02M2001/0054
摘要： The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n-type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.
摘要翻译：本发明提供一种用于功率转换的开关装置（100），其中具有n型发射极区（3）的第一栅电极（6），p型沟道层（2），第二栅电极（13），并且在n型半导体衬底（1）的表面侧依次重复布置p型浮动层（15）。夹着p型沟道层（2）的两个栅极（6,13）之间的间隔a被配置为小于夹着p型浮动层的两个栅极（13,6）之间的间隔b 15）。第一栅电极（6）和第二栅电极（13）都被提供有驱动定时具有时差的驱动信号。

85. 发明授权

US09159825B2 Double-sided vertical semiconductor device with thinned substrate 有权
标题翻译：双面垂直半导体器件，具有薄的衬底
公开(公告)号：US09159825B2
公开(公告)日：2015-10-13
申请号：US13860371
申请日：2013-04-10
申请人： Silanna Semiconductor U.S.A., Inc.
发明人： Stuart B. Molin , Michael A. Stuber
IPC分类号： H01L21/84 , H01L29/78 , H01L29/66 , H01L21/8234 , H01L29/73 , H01L29/732 , H01L29/739 , H01L29/744 , H01L27/082 , H01L27/088 , H01L29/06 , H01L21/683 , H01L29/417 , H01L29/423 , H01L23/00
CPC分类号： H01L27/0823 , H01L21/6835 , H01L21/823487 , H01L23/481 , H01L24/05 , H01L24/11 , H01L24/13 , H01L27/088 , H01L29/0657 , H01L29/0696 , H01L29/1095 , H01L29/41741 , H01L29/4236 , H01L29/66272 , H01L29/66333 , H01L29/66363 , H01L29/66666 , H01L29/66712 , H01L29/66734 , H01L29/73 , H01L29/7317 , H01L29/732 , H01L29/7394 , H01L29/7395 , H01L29/744 , H01L29/7802 , H01L29/781 , H01L29/7812 , H01L29/7813 , H01L29/7827 , H01L2221/68327 , H01L2221/6834 , H01L2224/0401 , H01L2224/056 , H01L2224/05638 , H01L2224/1148 , H01L2224/1302 , H01L2224/13022 , H01L2224/13023 , H01L2224/131 , H01L2224/13147 , H01L2224/48 , H01L2924/12042 , H01L2924/1301 , H01L2924/1304 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2924/00015 , H01L2924/01014 , H01L2924/00
摘要： A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.
摘要翻译：在具有第一表面，第二表面和背景掺杂的半导体层中形成垂直半导体器件。在半导体层的第二表面形成掺杂到与背景相反的导电类型的第一掺杂区域。在第一掺杂区域的内部，在半导体层的第二表面形成与背景相同导电类型的第二掺杂区域。半导体层的一部分在第一表面被去除，暴露出新的第三表面。第三掺杂区域形成在第三表面的半导体层的内部。至少对第二掺杂区域（经由第二表面）和第三掺杂区域（经由新的第三表面）进行电接触。以这种方式，可以在减薄的半导体或SOI层中制造垂直DMOS，IGBT，双极晶体管，晶闸管和其他类型的器件。

86. 发明授权

US09111898B2 Multiple layer substrate 有权
标题翻译：多层基板
公开(公告)号：US09111898B2
公开(公告)日：2015-08-18
申请号：US13770438
申请日：2013-02-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Long-Shih Lin , Fu-Hsiung Yang , Kun-Ming Huang , Ming-Yi Lin , Paul Chu
IPC分类号： B32B9/04 , B32B13/04 , H01L21/02 , H01L29/36 , H01L29/66 , H01L29/739 , H01L29/06 , H01L21/762
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/02488 , H01L21/0257 , H01L21/02587 , H01L21/76262 , H01L29/0619 , H01L29/36 , H01L29/66325 , H01L29/7394
摘要： A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.
摘要翻译：用于集成电路的衬底包括具有原始载流子浓度的器件晶片和设置在器件晶片上的外延层。外延层具有第一载流子浓度。第一载流子浓度高于原载流子浓度。

87. 发明授权

US09076837B2 Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage 有权
标题翻译：具有低寄生BJT增益和稳定阈值电压的横向绝缘栅双极晶体管结构
公开(公告)号：US09076837B2
公开(公告)日：2015-07-07
申请号：US13543662
申请日：2012-07-06
申请人： Long-Shih Lin , Kun-Ming Huang , Ming-Yi Lin
发明人： Long-Shih Lin , Kun-Ming Huang , Ming-Yi Lin
IPC分类号： H01L29/49 , H01L29/739 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423
CPC分类号： H01L29/66325 , H01L21/8222 , H01L29/0634 , H01L29/0696 , H01L29/0808 , H01L29/0847 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66931 , H01L29/7393 , H01L29/7394 , H01L29/7816 , H01L29/7824 , H01L29/7835
摘要： A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.
摘要翻译：本公开提供了金属氧化物半导体横向扩散器件（HV LDMOS），特别是横向绝缘栅双极结型晶体管（LIGBT）及其制造方法。该器件包括具有漂移区的漂移区绝缘体（SOI）衬底，漂移区中的两个相对掺杂的阱区，漂移区和第二阱区中的两个绝缘结构，第二阱区，栅极结构和源极在第二阱区域中的第三阱区域中嵌入第二阱区域。第三阱区域设置在栅极结构和第二绝缘结构之间。

88. 发明申请

US20150140741A1 Fully Isolated LIGBT and Methods for Forming the Same 审中-公开
标题翻译：完全隔离的LIGBT及其形成方法
公开(公告)号：US20150140741A1
公开(公告)日：2015-05-21
申请号：US14559674
申请日：2014-12-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
IPC分类号： H01L29/66 , H01L21/265 , H01L21/76 , H01L21/304
CPC分类号： H01L29/66325 , H01L21/265 , H01L21/304 , H01L21/76 , H01L21/761 , H01L21/76224 , H01L29/0696 , H01L29/7393 , H01L29/7394
摘要： A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.
摘要翻译：一种器件包括电介质层和介电层上的重掺杂半导体层。重掺杂半导体层是第一导电类型。半导体区域在重掺杂半导体层之上，其中半导体区域是与第一导电类型相反的第二导电类型。横向绝缘栅双极晶体管（LIGBT）设置在半导体区域的表面。

89. 发明申请

US20140235058A1 Method for Forming a Power Semiconductor Device 有权
标题翻译：形成功率半导体器件的方法
公开(公告)号：US20140235058A1
公开(公告)日：2014-08-21
申请号：US14260352
申请日：2014-04-24
申请人： Infineon Technologies Austria AG
发明人： Anton Mauder , Hans-Joachim Schulze , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Helmut Strack
IPC分类号： H01L21/28
CPC分类号： H01L21/28194 , H01L21/02109 , H01L21/02145 , H01L21/0228 , H01L29/0653 , H01L29/0878 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/407 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/513 , H01L29/66734 , H01L29/7393 , H01L29/7394 , H01L29/7397 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L29/7835 , H01L29/792 , H01L29/8611
摘要： A method for forming a semiconductor device includes providing a semiconductor body which has a main surface and a first n-type semiconductor region, forming a trench which extends from the main surface into the first n-type semiconductor region, and forming a dielectric layer having fixed negative charges on a surface of the trench, by performing at least one atomic layer deposition using an organometallic precursor.
摘要翻译：一种形成半导体器件的方法包括：提供具有主表面和第一n型半导体区域的半导体本体，形成从主表面延伸到第一n型半导体区域的沟槽，以及形成具有通过使用有机金属前体进行至少一个原子层沉积，在沟槽的表面上固定负电荷。

90. 发明申请

US20140042462A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140042462A1
公开(公告)日：2014-02-13
申请号：US14055615
申请日：2013-10-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshinori TSUCHIYA
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/046 , H01L21/0485 , H01L29/045 , H01L29/1608 , H01L29/51 , H01L29/66068 , H01L29/7394 , H01L29/7827
摘要： A semiconductor device according to the present embodiment includes a semiconductor substrate having a first n-type silicon carbide layer and a second n-type silicon carbide layer, a first p-type impurity region formed in the n-type silicon carbide layer, a first n-type impurity region of 4H—SiC structure formed in the n-type silicon carbide layer, a second n-type impurity region of 3C—SiC structure formed in the n-type silicon carbide layer having a depth shallower than the first n-type impurity region, a gate insulating film, a gate electrode formed on the gate insulating film, and a metallic silicide layer formed above the first n-type impurity region and having a bottom portion and a side surface portion such that the second n-type impurity region is sandwiched between the first n-type impurity region and at least the side surface portion.
摘要翻译：根据本实施例的半导体器件包括具有第一n型碳化硅层和第二n型碳化硅层的半导体衬底，形成在n型碳化硅层中的第一p型杂质区，第一形成在n型碳化硅层中的4H-SiC结构的n型杂质区，在n型碳化硅层中形成的深度比第一n-型碳化物深度浅的3C-SiC结构的第二n型杂质区，栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和形成在第一n型杂质区域上方的金属硅化物层，并且具有底部和侧表面部分，使得第二n型杂质区域杂质区域夹在第一n型杂质区域和至少侧面部分之间。

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